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TMC4361 datasheet cost - effective s - ramp motion controller for stepper motors - optimized for high velocities. with spi and step/dir interfaces to motor driver and encoder interface for closed loop operation a pplications textile, sewing machines factory automation lab automation medical office automation printer and scanner cctv, security atm, cash recycler pos pumps and valves heliostat controller cnc machines f eatures and b enefits 3.3v or 5v operation spi interface for c with easy - to - use protocol spi interface for spi moto r drivers step/dir interface step/dir motor drivers encoder i nterface: incremental abn and serial ssi/spi/biss 2x ref. - s witch input clock frequency up to 30 mhz different current l evels related to the motion profile status low power operation using clock gating technology s - shaped velocity ramps, optimally calculated linear ramps with trapezoid and rectangle shapes programmable microstep table on - the - fly ch ange of target motion parameters read - out option for all important motion parameters compact size 6x6 mm2 qfn40 package directly controls tmc23x, tmc24x, and tmc26x motor driver d escription the TMC4361 is intended for appl ications where a fast and jerk - limited motion profile is desired. this motion controller adds to any microcontroller with spi interface. it supports s - shaped, trapezoid, and rectangle ramps. with encoder, the TMC4361 allows for an extremely quick and preci se positioning. its servo features include no step - loss, energy efficiency, and target positioning with oscillation - free algorithms. standard spi and step/dir interfaces to the motor driver simplify communication. high end features without software effort and small form factor enable miniaturized designs with low external component count for cost - effective and highly competitive solutions. b lock d iagram s e r v o d r i v e t m c 4 3 6 1 s p i t o m a s t e r s a f e r a m p d o w n i s o 1 3 4 8 5 s t a t u s f l a g s i n t e r r u p t c o n t r o l l e r r e f . s w i t c h p r o c e s s i n g d r i v e r i n t e r f a c e : s p i / s t e p / d i r r e f . s w i t c h e s s - r a m p g e n e r a t o r i n c l . t r a p e z o i d , r e c t a n g l e , 4 b o w s s p i s t e p / d i r s p i t o c s d o t o c m u l i p l e x e d o u t p u t t i m e r u n i t p o w e r - o n r e s e t s t e p s e q u e n c e r c u r r e n t r e g u l a t i o n e n c o d e r i n t e r f a c e c l o s e d l o o p a b n s s i s p i b i s s c l k f r e e z e
high - end solution : velocity meets precision the TMC4361 is a miniaturized high performance stepper motor controller with an outstanding cost - performance ratio. it is designed for high volume as well as for demanding industrial motion control applications. the TMC4361 motion controller is equipped with an spi? host interface ( spi is t rademark of motorola) with easy - to - use protocol and two driver interfaces (spi and step/dir ) for addressing various stepper motor driver types. the TMC4361 scores with its unique servo drive features, high integration and a versatility that covers a wide spectrum of applications , motor sizes, and encoder types . for a comfortable handling, the chip provides the possibility to work with real world units. extensive support at the chip, board, and software levels enables rapid design cycles and fast time - to - market with competitive products. high energy efficiency delivers further cost savings. s - s haped v elocity p rofile this out standing ramp profile is completely jerk - free. seven segments of the ramp allow for an optimum adaption of the velocity profile to the customer specific application requirements. high torque with high velocities can be reached by calibrating the bows of th e ramp in a way that the acceleration value near v max is reduced in parallel to the available motor torque. s - shaped ramp profile c ompact d esign for r eliable c losed l oop o peration b enefit from high vel ocities combined wi th extremely high pr ecision ! closed loop operation is an optimum choice in case a dynamic and reliable drive without step - loss and motor stall is desired. the controller ic monitors the encoder values nonstop and uses them for a sophisticated motor field c ontrol. in case internal mosfets are desired, combine the TMC4361 with the tmc260, the tmc261 or the tmc2660. o rder c odes order code description size tmc 4361 - l a motion controller with servo and dcstep features , qfn 40 6 x 6 mm 2 v ( t ) t v m a x c t m c 2 4 8 m o t o r d r i v e r m o s f e t d r i v e r s t a g e h i g h l e v e l i n t e r f a c e m t m c 4 3 6 1 m o t i o n c o n t r o l l e r s p i s p i e n c o d e r a b n / s s i s p i / b i s s
table of contents 1 principles of operat ion ............... 5 1.1 k ey c oncepts ................................ ............ 5 2 pin assignments ................................ 6 2.1 p ackage o utline ................................ ...... 6 2.2 s ignal d escription ................................ . 6 3 sample circuits ................................ . 8 4 notes ................................ ....................... 9 5 spi control interfac e .................... 10 5.1 spi d atagram s tructure ....................... 10 5.2 spi s ignals ................................ .............. 11 5.3 t iming ................................ ....................... 12 6 input filtering ................................ .. 13 6.1 i nput f ilter c onfiguration ................... 13 7 status flags & event s .................... 16 7.1 s tatus f lags ................................ ............ 16 7.2 s tatus e vents & spi s tatus & i nterrupts ................................ ................................ . 16 7.3 i nterrupts ................................ ................ 17 8 ramp generator ................................ . 18 8.1 s tep /d ir o utput c onfiguration ............ 19 8.2 r amp m odes and t ypes ........................... 19 9 external step contro l - electronic gearing ................................ ................................ .. 26 10 reference switches .......................... 27 10.1 stopl and stopr ................................ .. 27 10.2 v irtual s top s witches ........................... 28 10.3 home r eference ................................ ...... 29 10.4 r epeating m otion after reaching xtarget ................................ ................................ . 30 10.5 c ircular movement ................................ .. 31 10.6 t arget r eached / p osit ion c omparison 33 11 ramp timing & synchr onization 34 11.1 s tart s ignal g eneration ....................... 34 11.2 s hadow r egister s et .............................. 38 11.3 t arget p ipeline ................................ ........ 41 11.4 p artitioned t arget p ipeline .................. 41 11.5 s ynchronizing s everal m otion c ontrollers ................................ ................................ . 44 12 serial data output .......................... 45 12.1 s ine w ave l ook - up t able ....................... 46 12.2 spi o utput p arameters .......................... 49 12.3 a utomatic cover datag rams .................. 50 12.4 c urrent d atagrams ................................ . 50 12.5 tmc m otor d river ................................ .. 51 12.6 c onnecting d river c hips from o ther p arties ................................ ................................ . 54 12.7 c urrent s caling & r amp s tatus ........... 55 13 nfreeze: emergency - stop ................ 58 13.1 f reeze f unction c onfiguration ............. 58 14 controlled pwm outpu t ................ 59 14.1 pwm o utput g eneration ....................... 5 9 15 support of the dcste p feature of tmc motor drivers ................................ ........... 61 15.1 e ssential pins and re gisters ................. 61 15.2 d esigning - i n dc s tep into an a pplication ................................ ................................ . 61 15.3 e nabling dc s tep ................................ ....... 62 16 decoder unit & close d loop ....... 64 16.1 g eneral e ncoder i nterface .................... 65 16.2 i ncremental abn e ncoder ..................... 65 16.3 a bsolute e ncoder ................................ .... 67 16.4 r egulation p ossibilities with e ncoder f eedback ................................ .................... 71 16.5 c ompensation of e ncoder m isalignments ................................ ................................ . 77 17 serial encoder outpu t unit ........ 78 17.1 p roviding ssi o utput d ata ................... 78 18 clk ga ting ................................ ............. 79 18.1 c lock g ating and w ake - up .................... 79 19 registers and switch es ................. 81 19.1 g eneral c onfiguration ........................... 81 19.2 r eference s witch c onfiguration .......... 83 19.3 s tart s witch c onfiguration ................. 85 19.4 i nput f ilter c onfiguration ................... 86 19.5 spi - o ut c onfiguration .......................... 87 19.6 c urrent c onf iguration ........................... 89 19.7 c urrent s cale v alues .............................. 89 19.8 e ncoder s ignal c onfiguration ............. 90 19.9 s erial e ncoder d ata in ......................... 92 19.10 s erial e ncoder d ata out ...................... 92 19.11 m otor d river s ettings ........................... 92 19.12 e vent s election r egisters ...................... 92 19.13 s tatus e vent r egister ............................. 93 19.14 s tatus f la g r egister .............................. 94 19.15 v arious c onfiguration r egisters ......... 95 19.16 r amp g enerator r egisters ..................... 96 19.17 t arget and c ompare r egisters .............. 98 19.18 p ipeline r egisters ................................ .... 98 19.19 s hadow r egisters ................................ ... 99 19.20 f reeze r egister ................................ ......... 100 19.21 c lock g ating e nable r egister ............... 100 19.22 e nco der r egisters ................................ ... 101 19.24 pid and c losed l oop r egisters ............ 102 19.25 m isc r egisters ................................ ......... 103 19.26 t ransfer r egisters ................................ .. 105 19.27 s in lut r egisters ................................ ..... 106 19.28 v ersion r egisters ................................ .... 107
20 absolute maximum rat ings ......... 108 21 electrical character istics .......... 108 21.1 dc c haracteristics o perating c onditions 108 21.2 p ower d issipation ................................ .. 109 21.3 g eneral io t iming p arameters ............. 110 22 modifications as reg ards TMC4361 (old version) ................................ ...................... 111 23 layout example ................................ .. 112 24 package mechanical d at a ............ 114 24.1 d imensional d rawings .......................... 114 24.2 p ackage c odes ................................ ......... 114 25 di sclaimer ................................ ............ 115 26 esd sensitive device ........................ 115 27 table of figures ................................ 116 28 revision history ............................... 117 28.1 d ocument r evisions ................................ 117
motion controller for stepper motors integrated circuits trinamic motion contr ol gmbh & co. kg hamburg, germany 1 principles of operation figure 1 . 1 basic application block diagram 1.1 key concepts the TMC4361 realizes real time critical tasks autonomously and guarantees for a robust and reliable drive. the following features contribute toward greater precision, greater efficiency, higher reliability, higher velocity, and s moother motion in many stepper motor applications. interfacing the TMC4361 offers application specific interfacing via step/dir or spi. initialization adapt the TMC4361 to the driver type and configuration and send initial configuration data to spi drivers . configure microstep resolution and waveform for spi drivers. positioning the TMC4361 o perates motor based on user specified target positions and velocities. modify all motion target parameters on - the - fly during motion. microstepping based on internal pos ition counters the TMC4361 performs up to 2 31 (micro)steps completely independent from the microcontroller. microstep resolutions are individually programmable. the range goes from full stepping (1 microstep = 1 full step) and half stepping (2 microsteps per full step) up to 8 bit micro stepping (256 microsteps per full step) for precise positioning and noiseless stepper motor rotation. with step/dir drivers any microstep resolution is possible as supported by the driver. the internal microstep table can b e adapted to specific motor characteristics to further reduce torque ripple, if desired. servo drive the TMC4361 provides closed loop operation for step/dir and spi drivers. using a differential or serial encoder, the closed loop unit of the TMC4361 compar es the external position counter values with the internal ones and sends signals for correction. chopsync? the TMC4361 has an i ntegrated chopsync chopper for very smooth motor movement. programming every parameter can be changed at any time. the uniform a ccess to any TMC4361 register simplifies application programming. a read - back option for nearly all internal registers is available. synchronization the TMC4361 provides synchronizing several TMC4361 motion controller chips if it is desired to move sever al motors simultaneously. s p i r e s n s c s i n s c k i n s d i i n s d o i n h o s t c p u s p i i n t e r f a c e r e g i s t e r b l o c k s t o p l s t o p r v d e c o d e r u n i t s c l k s c l k a n e n c o d e r ( d i f f e r e n t i a l ) s t e p / d i r o u t p u t i d i r o u t s t p o u t n s t d b y _ o u t o i n t r h o m e _ r e f s c a n t e s t i t e s t _ m o d e i s d o d r v s c k d r v s d i d r v n s c s d r v s p i d a t a g r a m g e n e r a t o r c l k - o u t c h o p s y n c c l k s t a r t s d i s d i b c l k _ e x t o i o i i o o o s p i o u t p u t i i i r e f e r e n c e p r o c e s s i n g o o i s t a r t / s t o p / r e f e r e n c e s w i t c h e s s e r i a l e n c o d e r u n i t r a m p s t a t u s i i i o n s c s n s c l k a n e g n n e g e x t e r n a l p o s c o u n t e r m a s t e r c l k s s i i n t e r n a l p o s e x t e r n a l p o s i o o r p o s c o u n t e r p w m u n i t s c a l e u n i t s c l k n s c l k s d o n s d o p w m a ( s i n e ) p w m b ( c o s i n e ) s e r i a l e n c o d e r p w m o u t p u t g n d ( 4 x ) v c c ( 3 x ) o r o r o r o r o r o r i o i n r s t v d d 1 v 8 ( 2 x ) t a r g e t r e g i s t e r ( s ) t i m e r u n i t c l k _ i n t s t a t u s f l a g s + e v e n t s i n t e r r u p t c o n t r o l c l k g a t i n g p a r a m e t e r s f r o m / f o r a l l u n i t s o t a r g e t _ r e a c h e d p o r p u l s e g e n c l o s e d l o o p u n i t c o m p a r e i n t e r n a l ( c o ) s i n e l u t i n t e r n a l s t e p c h o p s y n c u n i t a c t u a l c o - / s i n e v a l u e s c o m m u t a t i o n a n g l e c l o s e d l o o p s c a l i n g p w m o r d a c e n c r y p t e d c o - / s i n e v o l t a g e v a l u e s s t d b y s i g n a l o r s c a l e d c u r r e n t v a l u e s c o v e r r e g d r v t y p e f s d a t a o u t s s i s d o n s d i b n e g d a c a ( s i n e ) d a c b ( c o s i n e ) d a c o u t p u t o r n f r e e z e i i m m e d i a t e f r e e z e o f o p e r a t i o n d a c u n i t i o a b n s s i o r s p i o r i s s i s p i a b n p i d p i d _ e r a m p - g e n e r a t o r s - r a m p s w i t h 4 b o w s , t r a p e z o i d , r e c t a n g l e , . . .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 6 www.trinamic.com 2 p in assignments 2.1 package outline figure 2 . 1 pinning (top view) 2.2 signal description pin number type function gnd 6, 15, 25, 36 gnd digital ground pin for ios and digital circuitry v cc 5, 26, 37 vcc digital power supply for ios and digital circuitry (3.3v 5v) vdd1v8 16, 35 vdd connection of internal generated core voltage of 1.8v nscsin 2 i low active chip select input of the spi interface to the c sckin 3 i serial clock for the spi interface to the c sdiin 4 i serial data input of the spi interface to the c sdoin 7 o serial data output of the spi interface to the c ( z if nscsin= 1 ) clk_ext 38 i clock in put to provide an clock with the frequency f clk for all internal operati ons. nrst 39 i (p u ) low active reset. if not connected , p ower - on - r eset and internal pull - up resistor will be active . test_mode 34 i te st mode input. vcc = 3.3v: t ie to low for normal operation . vcc = 5.0v: t ie to vdd1v8 for normal operation . intr 33 o interrupt output , programmable pd/pu for wired - and/or target_reached 31 o target reached output , programmable pd/pu for wired - and/or stdby_clk 32 o standby signal or internal clk output or chopsync output t m c 4 3 6 1 - l i q f n 4 0 6 m m x 6 m m 0 . 5 p i t c h 1 2 3 4 5 6 7 8 2 8 2 9 2 2 2 3 2 4 2 5 2 6 2 7 1 8 1 1 1 2 1 3 1 4 1 5 1 6 1 7 3 6 3 5 3 4 3 3 3 2 3 9 3 8 3 7 9 1 9 3 0 4 0 2 0 2 1 3 1 1 0 n s c s i n s c k i n v c c g n d s d i i n s d o i n a _ s c l k a n e g _ n s c l k b _ s d i m p 2 s t o p l h o m e _ r e f g n d v d d 1 v 8 s t o p r s t p i n d i r i n s t a r t n f r e e z e b n e g _ n s d i n r s t c l k _ e x t g n d v d d 1 v 8 v c c t e s t _ m o d e i n t r t a r g e t _ r e a c h e d s t d b y _ c l k m p 1 s c k d r v _ n s d o s d i d r v _ n s c l k v c c g n d s d o d r v _ s c l k s t p o u t _ p w m a d i r o u t _ p w m b n n e g n n s c s d r v _ s d o
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 7 www.trinamic.com pin number type function stopl 12 i (pd) left stop switch . e xternal si gnal to stop a ramp. if not connected , an internal pull - down resistor will be active . home_ref 13 i (pd) home reference signal input . e xternal signal for reference search. if not connected , an internal pull - down resistor will be active . stopr 14 i (pd) r ight stop switch . e xternal signal to stop a ramp. if not connected, an internal pull - down resistor will be active . stpin 17 i (pd) step input for external step control dirin 18 i (pd) direction input for external step control start 20 io start signal in put/output nfreeze 19 i (pu) low active safety pin to immediately freeze output operations. if not connected , an internal pull - up resistor will be active . n 21 i (pd) n signal input of incremental encoder input interface if not connected, an internal pul l - down resistor will be active . nneg 22 i (pd) negated n signal input of incremental encoder input interface if not connected, an internal pull - down resistor will be active . b sdi 10 i (pd) b signal input of incremental encoder input interface . serial da ta input signal of serial encoder input interface (ssi/spi) . if not connected, an internal pull - down resistor will be active . bneg nsdi sdo_enc 11 io negated b signal input of incremental encoder input interface . negated serial data input signal of ssi en coder input interface serial data output of spi encoder input interface . a sclk 40 io a signal input of incremental encoder interface . serial clock output signal of serial encoder interface (ssi/spi) . aneg nsclk nscs_enc 1 io negated a signal input of in cremental encoder interface . negated serial clock output signal of serial encoder interface . low active chip select output of spi encoder input interface . stpout pwma daca 24 o step output . first pwm signal (sine) . first dac output signal (sine) . dirout pwmb dacb 23 o direction output . second pwm signal (cosine) . second dac output signal (cosine) . nscsdrv pwmb sdo 30 o low active chip select output of spi interface to motor dr i v er. second pwm signal (cosine) to connect with phb (tmc23x/24x). serial data output of serial encoder output interface . sckdrv mdbn nsdo 29 o serial clock output of spi interface to motor driver . mdbn output signal for mdbn pin of tmc23x/24x. negated serial data output of serial encoder output interface . sdodrv pwma sclk 27 io serial data output of spi interface to motor driver . first pwm signal (sine) ) to connect with pha (tmc23x/24x). clock input of serial encoder output interface . sdidrv err nsclk 28 i (pd) serial data input of spi interface to motor driver . error input s ignal to with err (tmc23x/24x). negated clock input of serial encoder output interface mp1 8 i (pd) multipurpose pin 1: dc_in as external dcstep input control signal synchro_in as external synchronization input control signal mp2 9 io multipurpose pin 2: dcstep_enable as dcstep output control signal. synchro_in as synchronization inout control signal. spe_out as output signal to connect with spe pin (tmc23x/24x) pd: if n.c. ? pull - down; pu: if n.c. ? pull - up
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 8 www.trinamic.com 3 sample circuits the sample circuits show the connection of external components. figure 3 . 1 how to connect the TMC4361 (vcc = 3.3v) figure 3 . 2 how to connect the TMC4361 (vcc = 5v) s c k d r v _ n s d o s d o d r v _ s c l k s d i d r v _ n s c l k n s c s d r v _ s d o s d i i n n s c s i n s c k i n s d o i n t m c 4 3 6 1 s p i c o n t r o l i n t e r f a c e t o m i c r o c o n t r o l l e r s p i o u t p u t i n t e r f a c e t o m o t o r d r i v e r s t p o u t _ p w m a d i r p o u t _ p w m b s t e p / d i r i n t e r f a c e t o m o t o r d r i v e r h o m e s t o p l s t o p r a _ s c l k a n e g _ n s c l k b _ s d i b n e g _ n s d i n n n e g e n c o d e r i n p u t i n t e r f a c e f o r i n c r e m e n t a l a b n o r s e r i a l b i s s / s s i / s p i c l k _ e x t g n d + 3 . 3 v s t a r t s t a r t s i g n a l i n p u t o r o u t p u t i n t r i n t e r r u p t o u t p u t e x t . c l o c k t a r g e t _ r e a c h e d t a r g e t r e a c h e d o u t p u t n f r e e z e e m e r g e n c y s t o p s w i t c h 1 0 0 n f 1 0 0 n f 1 0 0 n f s t d b y _ c l k s t a n d b y c l o c k o u t p u t n r s t o p t i o n a l i n v . r e s e t i n p u t v c c t e s t _ m o d e v d d 1 v 8 v d d 1 v 8 s c k d r v _ n s d o s d o d r v _ s c l k s d i d r v _ n s c l k n s c s d r v _ s d o s d i i n n s c s i n s c k i n s d o i n t m c 4 3 6 1 s p i c o n t r o l i n t e r f a c e t o m i c r o c o n t r o l l e r s p i o u t p u t i n t e r f a c e t o m o t o r d r i v e r s t p o u t _ p w m a d i r p o u t _ p w m b s t e p / d i r i n t e r f a c e t o m o t o r d r i v e r h o m e s t o p l s t o p r a _ s c l k a n e g _ n s c l k b _ s d i b n e g _ n s d i n n n e g e n c o d e r i n p u t i n t e r f a c e f o r i n c r e m e n t a l a b n o r s e r i a l b i s s / s s i / s p i r e f e r e n c e s w i t c h e s c l k _ e x t g n d + 5 v s t a r t s t a r t s i g n a l i n p u t o r o u t p u t i n t r i n t e r r u p t o u t p u t e x t . c l o c k t a r g e t _ r e a c h e d t a r g e t r e a c h e d o u t p u t n f r e e z e e m e r g e n c y s t o p s w i t c h 1 0 0 n f 1 0 0 n f 1 0 0 n f s t d b y _ c l k s t a n d b y c l o c k o u t p u t n r s t o p t i o n a l i n v . r e s e t i n p u t v c c t e s t _ m o d e v d d 1 v 8 v d d 1 v 8
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 9 www.trinamic.com figure 3 . 3 TMC4361 with tmc2 6x stepper driver in spi mode or s/d mode figure 3 . 4 TMC4361 with tmc248 stepper driver in spi mode figure 3 . 5 TMC4361 with tmc2 1xx stepper driver in spi mode or s/d mode 4 notes register names are italicized with value register in capital letters and switches with small letters. pin names are written with capital letters. t m c 4 3 6 1 c s c k m o s i m i s o s s s c k i n s d o i n c l k c l k _ e x t n s c s i n s d i i n m 1 0 k n s c s d r v _ s d o s d o d r v _ s c l k s c k d r v _ n s d o s d i d r v _ n s c l k s t e p d i r c s n s c k s d i s d o t m c 2 6 x s t p o u t _ p w m a d i r p o u t _ p w m b s g _ t s t m p 1 t m c 4 3 6 1 c s c k m o s i m i s o s s s c k i n s d o i n c l k c l k _ e x t n s c s i n s d i i n s d o c s n s d i s c k t m c 2 4 8 m 1 0 k n s c s d r v _ s d o s d o d r v _ s c l k s c k d r v _ n s d o s d i d r v _ n s c l k s t d b y _ c l k o u t p u t f o r c h o p s y n c o s c 1 5 k 6 8 0 p f
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 10 www.trinamic.com 5 spi control interface t he TMC4361 uses 40 bit spi? datagrams for communication with a microcontroller. the bit - serial interface is synchronous to a bus clock. for every bit sent from the bus master to the bus slave, another bit is sent simultaneously from the slave to the master . communication between an spi master and the TMC4361 slave always consists of sending one 40 - bit command word and receiving one 40 - bit status word. the spi command rate typically comprises a few commands per complete motor motion. spi c ontrol interface p in name type remarks nscsin input chip select of the spi - c interface (low active) sckin input clock of the spi - c interface sdiin input data input of the spi - c interface sdoin output data output of the spi - c interface 5.1 spi datagram structure microco ntrollers which are equipped with hardware spi are typically able to communicate using integer multiples of 8 bit. the nscsin line of the tmc 4361 has to be handled in a way, that it stays active (low) for the complete duration of the datagram transmission. each datagram sent to the TMC4361 is composed of an address byte followed by four data bytes. this allows direct 32 bit data word communication with the register set of the TMC4361. each register is accessed via 32 data bits even if it uses less than 32 data bits. e ach register is specified by a one byte address: - for a read access the most significant bit of the address byte is 0. - for a write access the most significant bit of the address byte is 1. some registers are write only registers, most can b e read additionally, and there are also some read only registers. 5.1.1 selection of write / read (write_notread) the read and write selection is controlled by the msb of the address byte (bit 39 of the spi datagram). this bit is 0 for read access and 1 for write access. so, the bit named w is a write_notread control bit. the active high write bit is the msb of the address byte. thus , 0x80 has to be added to the address for a write access. the spi interface always delivers data back to the master, indepen dent of the w bit. the data transferred back is the data read from the address which was transmitted with the previous datagram, if the previous access was a read access. if the previous access was a write access, then the data read back mirrors the previo usly received write data. so, the difference between a read and a write access is that the read access does not transfer data to the addressed register but it transfers the TMC4361 spi d atagram s tructure msb (transmitted first) 40 bit lsb (transmitted last) 39 ... ... 0 ? ? ? ? 31 ... 0 ? ? w 38...32 31...28 27...24 23...20 19...16 15...12 11...8 7...4 3...0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 11 www.trinamic.com address only a nd its 32 data bits are dummies. f urther , the following read or write access delivers back data read from the address transmitted in the preceding read cycle. a ttention a read access request datagram uses dummy write data. read data is transferred back to the master with the subsequent read or write access. hence, reading multiple registers can be done in a pipelined fashion . data which will be delivered are latched immediately after the prior data transfer. whenever data is read from or written to the TMC4361, the msbs delive red back contain the spi status spi_status , whi ch is a number of eight status bits . the selection of these bits will be explained in chapter 7.2 . example : for a read access to the register ( xactual ) with the address 0x21, the address byte has to be set to 0x21 in the access preceding the read access. for a write access to the register ( vactual ), the address byte has to be set to 0x80 + 0x22 = 0xa2. for read access, the data bit might have any value , e.g., 0 . action data sent to tmc data received from tmc read xactual ? 0x2100000000 ? 0xss & unused data read xactual ? 0x2100000000 ? 0xss & x_actual write vactual := 0x00abcdef ? 0xa200abcdef ? 0xss & x_actual write vactual := 0x00123456 ? 0xa200123456 ? 0xss00abcdef *)s s : is a placeholder for the status bit s spi_status 5.1.2 data alignment all data are right aligned. some registers represent unsigned (positive) values; some represent integer values (sign ed) as twos complement numbers. s ingle bits or groups of bits are represented as single bits respectively as i nteger groups. 5.2 spi signals the spi bus on the TMC4361 has four signals: sck in C bus clock input sdi in C serial data input sdo in C serial data output ns cs i n C chip select input (active low) the slave is enabled for an spi transaction by a transiti on to low level on the chip select input nscsin. bit transfer is synchronous to the bus clock sckin, with the slave latching the data from sdiin on the rising edge of sckin and driving data to sdoin following the falling edge. the most significant bit is s ent first. a minimum of 40 sckin clock cycles is required for a b us transaction with the TMC4361. if less than 40 clock cycles are transmitted, the transfer will not be valid, even for a read access. however, sending only eight clock cycles can be useful t o obtain the spi status because it sends the status information back first . if more than 40 clocks are driven, the additional bits shifted into sdiin are shifted out on sdoin after a 40 - clock delay through an internal shift register. this can be used for daisy chaining multiple chips. nscsin must be low during the whole bus transaction. when nscsin goes high, the contents of the internal shift register are latched into the internal control register and recognized as a command from the master to the slave. if more than 40 bits are sent, only the last 40 bits received before the rising edge of nscsin are recognized as the command.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 12 www.trinamic.com 5.3 timing the spi interface is synchronized to the internal system clock, which limits the spi bus clock sckin to half of the syst em clock frequency. the signal processing of the spi inputs are supported with internal schmitt t rigger, but not with rc elements. to avoid glitches at the inputs of the spi interface between c and TMC4361, external rc elements have to be provided. figure 5 . 1 shows the timing parameters of an spi bus transaction and the table below specifies the parameter values . figure 5 . 1 spi timing spi interface timing ac - characteristics clock period: t clk parameter symbol conditions min typ max unit sckin valid before or after change of nscsin t cc 10 ns nscsin high time t csh *) min time is for syn chronous clk with sckin high one t ch before scsin high only t clk *) >2t clk + 10 ns sc kin low time t cl *) min time is for syn chronous clk only t clk *) >t clk + 10 ns sckin high time t ch *) min time is for syn chronous clk only t clk *) >t clk + 10 ns sckin frequency using external clock (example: f clk = 16 mhz) f sck assumes synchronous clk f c lk / 2 (8) mhz sdiin setup time before rising edge of sckin t du 10 ns sdiin hold time after rising edge of sckin t dh 10 ns data out valid time after falling sckin clock edge t do no capacitive load on sdoin t filt + 5 ns t clk = 1 / f clk n s c s i n s c k i n s d i i n s d o i n t c c t c c t c l t c h b i t 3 9 b i t 3 8 b i t 0 b i t 3 9 b i t 3 8 b i t 0 t d o t z c t d u t d h t c h
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 13 www.trinamic.com 6 input f il tering input signals can be noisy due to long cables and circuit paths. to prevent jamming , every input pin provides a schmitt trigger . additionally , several signal s are passed through a digital filter. particular input pins are separated into four filteri ng groups. each group can be programmed individually according to its filter characteristics. p ins and r egisters : i nput f iltering g roups pin n ame s type remarks a_sclk b_sdi n aneg_nsclk bneg_nsdi nneg input s encoder interface input pins stopl home_ref stopr input s reference input pins start input start input pin sdodrv_sclk sdidrv_nsclk input s master clock input interface pins for serial encoder stpin dirin inputs step/dir interface inputs pin n ame register address remarks input_filt_conf 0x 03 rw filter configuration for all four input groups 6.1 input filter c onfiguration e very filtering group can be configured separately with regard to input sample rate and digital filter length. 6.1.1 input sample r ate (sr) input sample rate = f clk ? 1 / 2 sr where sr (extended with the particular name extension) is in [0 7 ] . this means that every (2 sr ) th input bit will be considered for internal processing. s ample rate configuration sr value sample rate 0 f clk 1 f clk / 2 2 f clk / 4 3 f clk / 8 4 f clk / 16 5 f clk / 32 6 f clk / 64 7 f clk / 128
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 14 www.trinamic.com 6.1.2 digital f ilter l ength (filt_l) one bit is sampled within each (2 sr ) th input clock cycle . the filter length filt_l can be set within the range [0 7]. the filter length filt_l specifi es the number of sampled bits that must have the same voltage level to set a new input bit voltage level. configuration of digital filter length filt_l value filter length 0 n o filtering 1 2 equal bits 2 3 equal bits 3 4 equal bits 4 5 equal bits 5 6 equal bits 6 7 equal bits 7 8 equal bits 6.1.3 stepdir input filter (c hanges as regards TMC4361old ) the step/dir input filtering setup differs slightly from the other groups as the other four groups already complete the whole input_filt_conf register 0x03 . thus, it is possible to assign th e step/dir input group to one of the existing by setting the appropriate bit in front of the setup parameters. in the following illustration, the filter settings for step/dir interface input pins will be taken from the re ference input pin group. if no group is selected, step/dir will be assigned to the encoder input interface filter group automatically . figure 6 . 1 step/dir input pin filter settings will be derived from the reference input filter group : sr_ sdin = 6 , filt_l_ sdin = 3 (other input filter groups: sr_enc_in = 5, filt_l_enc_in = 6, sr_ref = 6, filt_l_ref = 3, sr_s = 2, filt_l_s = 4, sr_enc_out = 0, filt_l_enc_out = 0) 6.1.4 example s the following three examples depict the input pin filtering of three different input filtering groups. the voltage levels after passing the schmitt trigger are compared to the internal signals which are processed by the motion controller. the sample points are depicted as green dashed line s. r eference i nput p ins here, every second clock cycle is sampled. two sampled input bits must be equal to be a valid input voltage. figure 6 . 2 reference input pins: sr_ref = 1, filt_l_ref = 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 s e r i a l c l o c k i n p u t s 3 1 b i t s o f r e g i s t e r 0 x 0 3 : i n p u t f i l t e r g r o u p : f i l t e r p a r a m e t e r : e x a m p l e : 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 s t a r t i n p u t r e f e r e n c e i n p u t s e n c o d e r i n p u t s f i l t _ l _ e n c _ o u t s r _ e n c _ o u t f i l t _ l _ s s r _ s f i l t _ l _ r e f s r _ e n c _ r e f f i l t _ l _ e n c _ i n s r _ e n c _ i n = p o s s i b l e s e l e c t i o n b i t s t o a s s i g n s t e p / d i r i n p u t f i l t e r p a r a m e t e r c l k h o m e i n t e r n a l h o m e s i g n a l s t o p l i n t e r n a l l e f t s t o p s i g n a l
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 15 www.trinamic.com s tart i nput p in every fourth clock cycle is sampled and the sampled input bit is valid. figure 6 . 3 start input pin : sr_s = 2, filt_l_s = 0 e ncoder i nterface i nput p ins every clock c ycle bit is sampled. eight sampled input bits must be equal to be a valid input voltage. figure 6 . 4 encoder interface input pins: sr_enc_in = 0, filt_l_enc_in = 7 c l k s t a r t i n t e r n a l s t e p i n p u t s i g n a l s t a r t i n t e r n a l d i r i n p u t s i g n a l c l k b _ s d i i n t e r n a l b i n p u t s i g n a l n i n t e r n a l n s i g n a l
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 16 www.trinamic.com 7 status f lags & events the TMC4361 of fers several possibilities for velocity ramps . it combine s target positioning and velocity ramps without interventions in between . however, the microcontroller connected to the TMC4361 normally require s status information. therefore, TMC4361 provides 32 st atus flags and 32 status events. s tatus events can be configured customer specific and lead through using the interrupt output of the TMC4361 . further , the eight spi status bits sent with each spi datagram can be read out . p ins and r egisters : s tatus f lags and e vents pin names type remarks intr output interrupt output to indicate status events register name register address remarks general_conf 0x00 rw bits: 15, 29, 30 status_flags 0x0f r 32 status flags of the TMC4361 and the connected tmc m otor drive r chip events 0x0e r+c 32 events triggered by altered TMC4361 status bits spi_status_selection 0x0b rw selection of 8 out of 32 events for spi status bits event_clear_conf 0x0c rw exceptions for cleared event bits intr_conf 0x0d rw selection of 32 even ts for intr output 7.1 status flags s tatus bits of the status_flags register are specified in the register chapter (see 19 ) . 7.2 status events & spi status & interrupts s tatus f lags - s tatus e vents s tatus event s are triggered during t he transition process of status bit s from inactive to active level. status bits and status events are associated in different ways : - several status event s are associated with one status bit. - some status events show the status transition of one or more st atus bits out of a status bit group. t he motor driver flags , e.g., trigger only one motor driver event motor_ev in case one of the selected motor driver status flags become s active. - in case a flag consists of more than one bit , the number of associated ev ents that can be triggered corresponds to the valid combinations. the vel_state flag, e.g., has two bit but three associated velocity state events ( b 00/ b 01/ b 10). such an e vent is triggered if the associated combination switch es from inactive to active. - furthermore, some events have no equivalence in the status_ flags register ( e.g. , cover_done which indicates new data from the motor driver chip ) . a ttention the events register 0x0e is automatically cleared after reading the register subsequent to a n spi datagram request. h ow to avoid a lack of information the recognition of a status event can fail in case it is triggered right before or during the events register 0x0e becomes cleared. to prevent events from being cleared, the event_clear_conf registe r 0x0c can be assigned properly. just set the related event_clear_conf register bit position to 1. u p to eight events can be selected for permanent spi status report. therefore, select up to eight events by writing 1 to the specific bit positions of the s pi_status_selection register 0x0b . the bit position s are sorted according to the event bit positions in the event s register 0x0e . in case more than eight events are chosen , the first eight bits (starting from index 0 = lsb ) are forwarded as spi_status .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 17 www.trinamic.com 7.3 in terrupts similar to the event_clear_conf register and the spi_status_selection register, events can be selected using the intr_conf register 0x0d to be forwarded to the intr output . the active polarity of the intr output can be set with the intr_pol bit of the general_conf register 0x00 . the selected events will be ored to one signal. the intr output becomes active as soon as one of the selected events triggers. a ttention due to the importance of events for interrupt generation and spi status monitoring, i t is recommended to clear the events register 0x0e before starting regular operation by reading it . 7.3.1 connecting several intr pins the intr pin could be configured for one interrupt signal transfer of several TMC4361 interrupt signals to the c. therefore, set intr_ tr_ pu_pd_en = 1 of the general_conf register 0x00. per default then, the pin will work efficiently as wired - or due to the fact that during intr pin is inactive, the output is pulled weakly to the inactive pin level polarity. if the pin becomes ac tive, it will pulled strongly towards the active polarity. connecting several pins at one signal line for the c will result in polarity change of the whole signal line if one of the TMC4361 intr pins will be set active. by setting intr_as_wired_and = 1 o f the general_conf register 0x00, the signal line will act as wired - and . while no interrupt is active, the intr pin will be pulled strongly towards the inactive polarity. during the active state, the pin will be pulled weakly at active polarity. that way, the whole signal line will be pulled to active state if all pins are forwarding the active polarity.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 18 www.trinamic.com 8 ramp generator step generation is one of the main task s of a stepper motor motion controller. the internal ramp generator of the TMC4361 provides several ways of step generation in order to form different ramp types to fit for various applications . p ins and r egisters : r amp g enerator pin names type remarks stpout_pwma output step output signal dirout_pwmb output direction output signal register name re gister address remarks general_conf 0x00 rw ramp ge nerator affecting bits 0 ? 5 stp_length_add dir_setup_time 0x10 rw additional step length in clock cycles; 16 bits additional time in clock cycles when no steps will occur after a direction change; 16 bi ts rampmode 0x20 rw requested ramp type and mode; 3 bits xactual 0x21 rw current internal microstep position; signed ; 32 bits vactual 0x22 r current step velocity; 24 bits; signed ; no decimals aactual 0x23 r current step acceleration; 24 bits; signed ; no decimals vmax 0x24 rw maximum permitted or target velocity; signed ; 32 bits = 24+8 (24 bits integer part, 8 bits decimal places) vstart 0x25 rw velocity at ramp start; unsigned ; 31 bits =23+8 vstop 0x26 rw velocity at ramp end; unsigned ; 31 bits =23+8 vbreak 0x27 rw at this velocity value, the ac - /deceleration will change during trapezoidal ramps; unsigned ; 31 bits =23+8 amax 0x28 rw maximum permitted or target acceleration; unsigned ; 24 bits =22+2 (22 bits integer part, 2 bits decimal places) dmax 0x29 rw maximum permitted or target deceleration; unsigned ; 24 bits =22+2 astart 0x2a rw acceleration at ramp start or below vbreak; unsigned ; 24 bits =22+2 dfinal 0x2b rw deceleration at ramp end or below vbreak; unsigned ; 24 bits =22+2 bow1 0x2d rw first bow value of a complete velocity ramp; unsigned ; 24 bits =24+0 (24 bits integer part, no decimal places) bow2 0x2e rw second bow value of a complete velocity ramp; unsigned ; 24 bits =24+0 bow3 0x2f rw third bow value of a complete velocity ramp; unsigned ; 24 bits =24+0 bow4 0x30 rw fourth bow value of a complete velocity ramp; unsigned ; 24 bits =24+0 clk_freq 0x31 rw external clock frequency f clk ; unsigned ; 25 bits xtarget 0x37 rw target position; signed ; 32 bits
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 19 www.trinamic.com 8.1 step/dir output c onfiguration step/d ir out put signals can be configured for the driver circuit: - for s tep signals that have to be longer than one clock cycle set stp_length_add ( bit15:0 of register 0x10) appropriately . then, the resulting step length is equal to stp_length_add +1 clock cycles. thus , the step length can be chosen within the range 12 16 clock cycles. - dirout does not change the level during the active step pulse signal and for stp_length_add +1 clock cycles after the step signal return s to the in active level. - with the register dir_setu p_time ( bit31:16 of register 0x10) the delay [ clock cycles ] between dirout and stpout voltage level changes can be set. using this register, no steps are sent via stpout for dir_setup_time clock cycles after a level change at dirout. h ints - per default, t he step output is high active because a rising edge at stpout indicates a step. - for changing the polarity, set step_inactive_pol = 1 . now, each falling edge indicates a step. - a step can be generated by toggeling the step output. therefore, set toggle_step = 1. - per default, a positive internal velocity vactual will result in a forward motion through the internal sinlut. naturally, if vactual < 0, the sinlut values will be developed backwards. this relation could be altered by setting reverse_motor_dir = 1. - pol _dir_out sets the dirout output level for the negative velocity direction. dirout is based on the internal step position mscnt and therefore based on the sinlut. - pol_dir_out , step_inactive_pol (bit5) , reverse_motor_dir (bit28 ) , and toggle_step (bit 4 ) are part of the general configuration gen e ral_conf register 0x00 . 8.2 ramp m odes and t ypes with proper configuration, the internal ramp generator of the TMC4361 is able to generate various ramps and the related step output s for stpout. note, that there are many po ssibilities to combine a general ramp mode (velocity mode, positioning mode) with basic ramp type s ( ramp in hold mode, trapezoidal ramp , s - shaped ramp). therefore, select the general ramp mode and type first and proceed with further specifications, e.g., s etting start and stop velocities or choosing different acceleration/deceleration values for each ramp phase. g eneral r amp m odes two general ramp modes can be chosen with the rampmode register . therefore, bit2 of the rampmode register 0x20 is used: rampm ode(2)=0 velocity mode . the target velocity vmax will be reached using the selected ramp type. rampmode(2)=1 positioning mode . vmax is the maximum velocity value which will be used within the given ramp type and as long as the target position xtarget will not be exceeded. furthermore, the sign of vmax is not relevant during positioning. the direction of the steps depends on xactual , xtarget , and the current ramp status. r amp t ypes three basic ramp types are provided. these types differ in the velocity valu e development during the drive. for setting the basic ramp type, use the bits 1 and 0 of the rampmode register 0x20 : TMC4361 r amp t ypes ramp mode (1 : 0) ramp type function b ramp in h old mode follow vmax only (rectangle velocity shape) . b trapezoid al ramp consideration of acceleration and deceleration values without adaption of these values . b s - shaped ramp use all ramp values (including bow val ue s).
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 20 www.trinamic.com rampmode( 1 : 0 )= b 00 rectangle shaped ramp type in hold mode . vactual is set immediately to v max . figure 8 . 1 rectangle shaped ramp type ramp mode( 1 : 0 )= b 01 trapezoidal shaped ramp type figure 8 . 2 trapezoidal shaped ramp type this trapezoidal ramp type reaches vmax using linear ramps whereas the actual acceleration/deceleration factor aactual register depends on the current ramp phase and the velocity which shoul d be reached. the corresponding sign assignment for different ramp phases is depicted in the following table: ramp phase: a 1l a 1 a 2 a 3 a 3l v>0: aactual= astart amax 0 - dmax - dfinal v<0: aactual= - astart - amax 0 dmax dfinal a cceleration slope and deceleration slope have only one acceleration/deceleration value each. for this types, set vbreak = 0. the acceleration /deceleration factor alters at vbreak . in positioning mode , the ramp finish es exactly at the target position xtarget by keeping vactual = vmax as long as possible . in positioning mode ( rampmode ( 2)=1), vactual is set instantly to 0 if the target position is reached. for exact positioning, it is recommended to set vmax f clk ? 1/4 pulses v ( t ) t v m a x v ( t ) t v m a x a 1 a 2 a 3 v ( t ) t v m a x v b r e a k a 1 a 2 a 3 l a 1 l a 3
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 21 www.trinamic.com ramp mode( 1 : 0 )= b 10 s - shape d ramp types figure 8 . 3 s - shaped ramp without initial and final acceleration/deceleration values figure 8 . 4 s - shaped ramp type with initial acceleration and final deceleration value for b1 and b4 this ramp type reach es vmax by means of s - shaped ramps whereas the ac celeration /deceleration factor depends on the current ramp phase and alters every 64 clock c ycles during the bow phases b 1 , b 2 , b 3 , and b 4 . ramp phase: b 1 b 12 b 2 b 23 b 3 b 34 b 4 v>0: aactual= astart ? ? ? ? actual = bow1 0 - bow2 0 - bow3 0 bow4 v<0: aactual= - astart ? ? ? ? actual = - bow1 0 bow2 0 bow3 0 - bow4 s - shaped ramps in posi tioning mode the ramp finish es exactly at the target position by keeping abs( vactual ) = vmax as long as possible. furthermore, the slopes to and from vmax are as fast as possible w ithout exceeding given values. i t is even possible that the phases b 12 , b 23 , and b 34 are left out due to given values. nevertheless, the s - shaped ramp style is always performed in positioning mode, if ramp_mode( 1 : 0 ) = b 10 is set . a ttention the parameter dfinal is not considered during positioning mode! a ttention : do not switch the rampmode if vactual is not constant. also, do not switch to positioning mode if vactual 0 and the difference between xactual and xtarget is too small for the given falling sl ope. h int : there is o ne exception: i f circular mo v e ment (see 0 ) is enabled and current velocity is too high for exact positioning during one revolution, it is possible to change from velocity to position i ng mode . f astest poss ible slope in positi oning mode the fastest possible slopes are always performed if the phases b 12 and/or b 34 are not reached during a rising and/or falling s - shaped slope. thus, the ramp maintains the maximum velocity vmax as long as possible in positionin g mode until the falling slope finishes the ramp to reach xtarget exactly. the result is the fastest possible positioning ramp in matters of time. the s tart phase and the end phase of an s - shaped ramp can be accelerated /decelerated by astart and dfinal . using these parameters , the ramp starts with astart and it is ended with dfinal . dfinal becomes valid as soon as aactual reaches the chosen dfinal value. astart and dfinal can be set separately . v ( t ) t v m a x b 1 b 1 2 b 2 3 b 3 4 b 3 b 4 b 2 a s t a r t = 0 d f i n a l = 0 v ( t ) t v m a x b 1 b 1 2 b 2 3 b 3 4 b 3 b 4 b 2 a s t a r t > 0 d f i n a l > 0
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 22 www.trinamic.com 8.2.1 velocity start vstart and velocity stop vstop s - shaped and trapezoidal velocity ramps can be started with an initial velocity value b y setting vstart higher than zero (see figure 8 . 5 ) . such a n s - shaped ramp with vstart > 0 is a ramp without the first ramp bow b 1 . t he ramp starts with aactual = amax and vactual = vstart . logically, t he p arameter astart is not considered . it is also possible to set vstop ( a final velocity value ) which finish es the ramp if vactual reaches the vstop value (see figure 8 . 6 ) . this leads to a n s - shaped velocity ramp without the bow b 4 . hence, dfinal is not considered . t rapezoidal and s - shaped ramps using p arameter vstart vstart > 0 and vstop = 0 figure 8 . 5 trapezoidal and s - shaped ramps using vstart t rapezoidal and s - shaped ramps using p arameter vstop vstart = 0 and vstop > 0 figure 8 . 6 trapezoidal and s - shaped ramps using vst op t rapezoidal and s - shaped ramps using p arameters vstart and vstop vstart > 0 and vstop > 0 figure 8 . 7 trapezoidal and s - shaped ramps using vstart an d vstop v ( t ) t v m a x v b r e a k a 1 a 2 a 3 l a 1 l a 3 v s t a r t v ( t ) t v m a x b 1 b 1 2 b 2 3 b 3 4 b 3 b 4 b 2 v s t a r t v ( t ) t v m a x v b r e a k a 1 a 2 a 3 l a 1 l a 3 v s t o p v ( t ) t v m a x b 1 b 1 2 b 2 3 b 3 4 b 3 b 4 b 2 v s t o p v ( t ) t v m a x v b r e a k a 1 a 2 a 3 l a 1 l a 3 v s t o p v s t a r t v ( t ) t v m a x b 1 b 1 2 b 2 3 b 3 4 b 3 b 4 b 2 v s t o p v s t a r t
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 23 www.trinamic.com s uggestions - vstart and vstop can only be used to start or end a velocity ramp. if the velocity direction alters due to register assignments while a velocity ramp is in progress , the velocity values develop according to the current velocity ramp type without using vstart or vstop . - vstop can be used in positioning mode if the target position is reached . in velocity mode, vstop can only be used if vactual 0 and the target velocity vmax is assigned to 0. - the unsigned values vstart and vstop are valid for both velocity directions. - every register value change is assigned immediately. a ttention vbreak must set higher than vstop , except is it not used ( vbre ak =0)! u sing vstart and astart concurrently for s - shaped ramps ( not implemented for TMC4361 old ) in some s - shaped ramp applications, it could be useful to start with a defined velocity value ( vstart > 0), but not with the maximum acceleration value amax . thus, use_astart_and_vstart (bit0 of the general_conf register 0x00 ) have to be set to 1. as a result, the following special ramp types are also possible. f igure 8 . 8 s - shaped ramps using vstart > 0 and us e _ astart _ and _ vstart = 1 . a s a result , section b 1 will be passed throu gh , although vstart is used . a ttention if the requested conditions for the acceleration slope of an s - shaped ramp ( vstart and astart , bow1 and bow2 ) do not fit with vmax , the starting ac celeration value is altered. note that not correctly adjusted values can lead to an acceleration slope with a final velocity after b2 greater than vmax . in this case the given vmax will be initiated by a falling slope to vmax after finishing the accelerati on slope. in case only one of the parameters vstart and astart is used, the v ( t ) v m a x b 1 b 1 2 b 2 3 b 3 4 b 3 b 4 b 2 v s t o p v s t a r t a s t a r t = 0 v ( t ) t v m a x b 1 b 1 2 b 2 3 b 3 4 b 3 b 4 b 2 v s t o p v s t a r t a s t a r t > 0
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 24 www.trinamic.com 8.2.2 internal ramp generator units all parameter units are real arithmetical units. therefore, it is necessary to set the clk_freq register to the appropriate value in [hz] which is given by the external clock. any value b etween 4.2 mhz and 32 mhz could be chosen. v elocity values vactual is given as a 32 bit signed value with no decimal places . the unsigned velocity values vstart , vstop , and vbreak consist of 23 digits and 8 decimal places. vmax is a signed value with 2 4 digits and 8 decimal places. velocity values are given in pulses per second [pps]. a ttention the maximum velocity vmax is restricted by the clock frequency. values higher than ( ? puls C f clk ) are prohibited because of an incorrect stpout output if vactual exceeds this limit. a cceleration values the unsigned values amax , dmax , astart , and dfinal consist of 22 digits and 2 decimal places . aactual shows a 24 bit non decimal signed value. acceleration and deceleration un its are given in pulses per second2 [pps2]. b ow parameter values bow values are unsigned 24 bit values without decimal places. they are given in pulses per second3 [pps3]. the following absolute minimum and maximum values are valid : value classes veloci ty acceleration bow clock registers vmax, vstart, vstop, vbreak amax, dmax, astart, dfinal bow1, bow2, bow3, bow4 clk_freq ( f clk ) minimum 3.906250 mpps 0.250000 m pps 2 1 pps 3 4.194304 mhz maximum 8.388607 pps ? puls * f clk 4.194303 pps 2 16.777 pps 3 30 mh z s hort and s teep r amps for short and steep ramps higher acceleration/deceleration and bow values than usual are available by activating direct_acc_val_en and direct_bow_val_en (bit1 and bit2 of the general_conf register 0x00 ). set these parameters to 1 t o change the units : direct_acc_val_en =1 t he values for amax , dmax , astart , dfinal , and dstop ( see chapter 0 ) are given as velocity value change per clock cycle with 24 bit unsigned decimal places ( msb = 2 - 14 ) . direct_bow_val_ en =1 b ow values are given as acceleration value change per clock cycle. the values bow1 , bow2 , bow3 , and bow4 are 24 bit unsigned decimal places with the msb defined as 2 - 29 . e xample with a clock frequency f clk = 16 mhz the following maximum values are val id : value classes acceleration ( direct_acc_val_en = 1) bow ( direct_bow_val_en =1 ) registers amax, dmax, astart, dfinal, dstop bow1, bow2, bow3, bow4 calculation a[pps2] = ( ? 37 ? f clk 2 bow[pps3] = ( ?a 53 ? f clk 3 minimum ~1.86 kpps2 ~454.75 kpps3 maximum ~31.25 gpps2 ~7.63 tpps 3
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 25 www.trinamic.com 8.2.3 limitations for on - the - fly changes of ramp parameters every register value change is assigned immediately. excepti ons will be explained in chapter 11 . generally, following ramp parameters should only be changed if vactual = 0 and no motion has been started so far: - vstart , vstop , vbreak - amax , dmax , astart , dfinal - bow1 , bow2 , bow3 , bow4 a t tention it is also possible, but not recommended , to change these parameters during motion (preferably if vactual is constant). if these register value will be changed during motion, internal re e valuations could cause temporary ramp abortions in the way of the given ramp type , vmax overshooting (in velocity and positioning mode) or target position overshooting (in positioning mode). for these reasons, changing the mentioned ramp parameters during motion should be carefully evaluated for every possible occur rence in the application run. r ampmode changes 1.) it is not recommended to switch the rampmode register if vactual is not constant. 2.) furthermore, switching to positioning mode should always assigned if vatual = 0. 3.) whereas, switching to velocity mode could also made during motion if the ramp type is not changed ( rampmode (2) = constant!) . 4.) these rules are also valid for rampmode changes initiated by the timer unit (see chapter 11 ) 5.) if circular movement is enabled (see section 0 ), switching to positioning mode could also assigned during motion if a ssigning vmax and xtarget during motion in v elocity m ode obviously, it is possible to change xtarget at any time during velocity mode as the target position will be not the determining factor for the motion run. as the velocity mode will constantly follow the currently assigned vmax value, there are no restrictions as regards the point in time when vmax will be changed. please, note that vstart resp. vstop for tra pezoidal and s - shaped ramps will only be used if vactual = 0 and vmax 0 resp. vactual 0 and vmax = 0. a ssigning vmax during motion in pos itioning m ode vmax could be set at any time during motion in positioning mode. TMC4361 will then use the given parameter to reach as fast as possible the newly given velocity limit vm ax, but considering always xtarget which will be determining factor during positioning mode.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 26 www.trinamic.com 9 external step control - electronic gearing steps could also generated by external steps which are manipulated internally by an electronic gearing. this featur e is not available for TMC4361old. p ins and r egisters : e xternal step c ontrol pin names type remarks stpin in put step input signal dirin in put direction in put signal register name register address remarks general_conf 0x00 rw bits : 6 ? 9 , 26 gear_rati o 0x 12 rw electronic gearing factor; signed; 32 bits =8+24 (8 bits integer part, 24 bits decimal places) to synchronize with other motion controllers TMC4361 offers a step direction input interface. by setting sdin_mode b00 (bit7:6 of the general_conf register 0x00 ) , the s/d input interface will be enabled which will disable concurrently the internal ramp generator. the polarity of the stpin input could be assigned by setting sdin_mode = b01 for a high active step polarity and b10 for a low active stp in input. if sdin_mode is set to b11 , every voltage level transition at stpin will be taken as single step. the polarity of dirin could be set by pol_dir_in ( bit 8 of general_conf register 0x00) whereas the negative direction will be assigned directly wit h this switch . if an external step is not congruent with an internal step, gear_ratio register 0x12 have to be set accordingly. this signed parameter consists of eight bit digits and 24 bits decimal places. with every external step the chosen value of ge ar_ratio will be added to an internal accumulation register. if an overflow will occur an internal step will be generated and the remainder will be kept for the next external step. thus, any absolute gearing value between 2^ - 24 and 127 is possible. gearing ratios beyond 1 are more reasonable for the spi output which uses the internal sinlutable because multiple steps will be generated one after another without interpolation if the accumulation register has a value above 1. in contrasts to a burst of steps a t the s tpout pin, the spi output will only forward the new position in the inner sinlut where only some values have been skipped if | gear_ratio | > 1. if the gearing factor is a negative number, the direction which are given by dirin and pol_dir_in will b e inverted. by setting sd_indirect_control = 1 (bit9 of the general_conf register 0x00 ) , the internal ramp generator is enabled due to the fact that external step impulse s transferred via stpin and dirin will not influence the internal xactual counter dir ectly. instead, the xtarget register will be altered by 1 with every gear_ratio accumulation register overflow. if xtarget will be increased or decreased depends (in the same way as known from the direct control) on the sign of the gear_ratio , pol_dir_in , and dirin when the accumulation overflow appears. the usage of this feature allows a synchronized motion of different velocity ramps where every ramp follows its own parameters. s witching between dir ect external control and internal ramp ge neration during the direct external control ( sdin_mode b00 and sd_indirect_control = 0 ), the internal ramp generator will be switched off. however, if automatic_direct_sdin_switch_off (bit26 of the general_conf register 0x00) is set to 1, a fluent transfer from direct external control to an internal ramp co uld be managed. if this mode is active, vstart will define the actual velocity value if direct external control is switched off. the internal direction will be selected automatically. the time step of the last internal step will also taken into account to provide a smooth transition from external to internal ramp control. thus, the only parameter which has to be set externally is vstart whose value should be know by the connected c. to support also a smooth s - shaped ramp transition, the starting accelerati on value could also be set separately. by setting astart 0, the internal ramp will start with aactual = astart if a_sign_bit = 0 or aactual = - astart if a_sign_bit = 1. th is a_sign_bit (bit31 of astart register 0x2a) have to be set also because there is no calculation of the external velocity which is a requirement for an automatic setting of the sign bit. a detailed example will be provided in chapter which illustrates the usage of the introduced parameters for external control and the automatic switch off.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 27 www.trinamic.com 10 reference switches the r eference input signals of the TMC4361 can be considered as a safety feature . the TMC4361 provides different possibilities for reference switch es and allow s for appropriate settings for various applications . the TMC4361 offers two switches in hardware (stopl, stopr) and two additional virtual stop switches ( virt_stop_left, virt_stop_right) . additionally, an home reference switch is available. digital filter settings for the reference switches could be assigned in the filter con figuration register. a limitation of xactual will be supported also to offer an easy implementation of circular motion profiles. p ins and r egisters : r eference s witches pin names type remarks stopl input left reference switch stopr input right reference s witch home_ref input home switch target_reached output reference switch to indicate xactual = xtarget register name register address remarks general_conf 0x00 rw bits: 16, 27, 29, 31 reference_conf 0x01 rw configuration of interaction with reference p ins home_safety_margin 0x1e rw region of uncertainty around x_home dstop 0x2c rw deceleration value if stop switches stopl/stopr or virtual stops are used with soft stop ramps. the deceleration value allows for an automatic linear stop ramp. pos_comp 0x 32 rw free configurable compare position; signed; 32 bits virt_stop_left 0x33 rw virtual left stop that triggers a stop event at xactual virt_stop_left; signed; 32 bits virt_stop_right 0x34 rw virtual left stop that triggers a stop event at xactual v irt_stop_right; signed; 32 bits x_home 0x35 rw home reference position; signed; 32 bits x_latch rev_cnt 0x36 r stores xactual at different conditions or revolution counter for circular movement; signed; 32 bits x_range w limit for internal positions; u nsigned; 31 bits circular_dec 0x7c w decimal places for circular movement 10.1 stopl and stopr a left and a right stop switch are provided in hardware in order to stop the drive im mediately, if one of them is triggered. therefore, pin 12 and pin 14 of the mot ion controller have to be used. both switches have to be enabled first: - to use stopl set stop_left_en = 1 (bit0 of reference_conf register 0x01) . now, the current velocity ramp stops in case stopl is equal to the chosen active polarity pol_stop_left (bit2 of reference_conf register 0x01) and vactual < 0. - to use stopr set stop_right_en = 1 (bit1 of reference_conf register 0x01) . now, stopr stops the ramp in case the stopr voltage level matches pol_stop_right (bit3 of reference_conf register 0x01) and vactua l > 0. the deceleration slope for stopping the ramp is influenced by soft_stop_en (bit 5 of reference_conf register 0x01) : - set soft_stop_en = 0 for a hard and quick stop . - set soft_stop_en = 1 to stop the ramp with a linear falling slope. in this case th e deceleration factor is determined by dstop . vstop is not considered during the stop deceleration slope. a ttention if dstop = 0 (default value!) and soft stop is enabled, the ramp will not stop due to the fact that the stop deceleration slope factor is 0 . further on, dstop could be altered during the stop slope to change the soft stop deceleration slope as requested.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 28 www.trinamic.com at the same time when a stop switch becomes active , the related status flag will be set and the particular e vent will be released . the flag remains set as long as the stop switch remains active. after reaching vactual = 0 due to the slope, further movement in the particular direction is not possible . driving on in the direction of a reference switch is possible if the following conditions are met: - t he related status event is set back. the reference switch is not active anymore or alternatively, t he related enabling switch ( stop_left_en , stop_right_en ) is re set to 0 (switched off) to go on driving in the - prior to that - closed direction. - s top even ts are cleared by reading out the events register 0x0e . this is done automatically by the m otion controller subsequent to an spi datagram r ead r equest to this register . (there is only one exception to this if an event is selected for the event_clear_c onf register in order to inhibit the regular clearing.) 10.1.1 latching c onfiguration s four different events can be chosen to latch the current internal position xactual in the register x_latch . therefore, bit13:10 of reference_conf register 0x01 have to be set a ccordingly. the f ollowing events and reference configurations result in such a transfer xlatch = xactual with an event indicating the latching process : reference c onfiguration pol_stop_left =0 pol_stop_left =1 pol_stop_right =0 pol_stop_right =1 latch_x_on_i nactive_l =1 stopl = 0 ? 1 stopl = 1 ? 0 --- --- latch_x_on_active_l =1 stopl = 1 ? 0 stopl = 0 ? 1 --- --- latch_x_on_inactive_r =1 --- --- stopr = 0 ? 1 stopr = 1 ? 0 latch_x_on_active_r =1 --- --- stopr = 1 ? 0 stopr = 0 ? 1 h int setting invert_stop_di rection =1 (bit 4 of reference_conf register 0x01) swap s stopl and stopr. thus, all configuration parameters for stopl become valid for stopr and vice versa. 10.2 virtual stop switches the TMC4361 provides additional virtual limits which trigger stop slopes in c ase the specific virtual stop switch microstep position is reached . virtual stop positions can be set using the virtual_stop_left and virtual_stop_r i ght registers 0x33 resp. 0x34 . virtual stop switches have to be enabled like non - virtual reference switch es. therefore, set virtual_left_limit_en (bit 6 of reference_conf register 0x01) resp . virtual_right_limit_en (bit 7 of reference_conf register 0x01) to 1. hitting a virtual limit switch triggers the same process as hitting stopl or stopr. at the same time when a virtual stop switch becomes active an event becomes released which has to be cleared in any case before further movement in the particular direction can be performed again. driving on in the direction of a virtual switch after a stop event is poss ible if the following conditions are met: - for further movement in negative direction choose a new value for virtual_stop_left or set virtual_left_limit_en = 0. it is not necessary to clear the event vstopl_active first. - for further movement in positive dir ection choose a new value for virtual_stop_r i ght or set virtual_right_limit_en = 0. it is not necessary to clear the event vstopr_active first. the deceleration slope can be chosen with virt_stop_mode (bit 9:8 of reference_conf register 0x01) : - set virt_st op_mode = b 01 for a hard and quick stop. - set virt_stop_mode = b 10 to stop the ramp with a linear falling slope. in this case the deceleration factor is determined by dstop . a ttention invert_stop_direction has no influence on virtual_stop_left resp. vir tual_stop_right !
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 29 www.trinamic.com 10.3 home r eference for monitoring , the switch reference input home_ref is provided. h oming p rocess - enable the tracking mode with start_home_tracking = 1 ( bit 20 of reference_conf register 0x01) . - w ith t he next home event xactual is latched to x_home . - the xlatch_done event will be released (not implemented for TMC4361old) and the switch start_home_tracking of the reference_conf register is automatically reset to 0 . - an error flag is permanently evaluated . this error flag indicates whether the c urrent voltage level of the home_ref reference input is valid in respect to x_home and the chosen home_event . nine different home events are possible. besides home_event = b 0000 which uses the n signal of an incremental abn encoder, the follo wing home ev ents can be used. therefore, configure the four home_event bits (bit 19:16 of reference_conf register 0x01) . ) home_event description x_home (direction: negative/positi ve) b b b b b b b b d efining an uncertainty area around x_home use the register home_safety_margin (0x1e) for defining an uncertainty area around x_home . then, homing uncertainties related t o the special application environment are considered for the further process. there will be no error flag generated if two conditions are met: xactual x_home - home_safety_margin and xactual x_home + home_safety_margin the following examples (see figure 10 . 1 .) show the points at which - dependent on the chosen home_event - an error flag is generated . t he following examples illustrate home_ref monitoring and generation of the home_error_flag for home_event = b 0011 (*), b 1100 (**), b 0110 (***), b 0010 (***), b 0100 (***), b 1001 (****), b 1011 (****), and b 1101 (****). figure 10 . 1 home_ref monitoring and home_error_flag h o m e _ r e f 0 1 h o m e _ r e f 0 1 h o m e _ r e f 0 1 h o m e _ r e f 0 1 h o m e _ r e f 0 1 h o m e _ r e f 0 1 h o m e _ r e f 0 1 h o m e _ r e f 0 1 h o m e _ e r r o r _ f l a g * * * h o m e _ r e f x _ h o m e h o m e _ s a f e t y _ m a r g i n h o m e _ e r r o r _ f l a g * h o m e _ e r r o r _ f l a g * * h o m e _ e r r o r _ f l a g * * * * x _ h o m e h o m e _ s a f e t y _ m a r g i n h o m e _ e r r o r _ f l a g * * * h o m e _ r e f h o m e _ e r r o r _ f l a g * h o m e _ e r r o r _ f l a g * * h o m e _ e r r o r _ f l a g * * * *
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 30 www.trinamic.com it is recommended to set the home_safety_margin bigg er than the period during which the home_ref level is active for the home_event s b 0110, b 0010, b 0100, b 1001, b 1011, and b 1101. this is necessary to avoid wrong home_error_flag s. after homing with the n channel ( home_event = b 0000) for a precise as signment of x_home the correct home_event has to be assigned in order to activate the generation of home_error_flag s. note that home_event = b 0000 results in home_error_flag = 0 permanently. a ttention in contrast to TMC4361old, it is not required to set latch_ x _on_n and c lr_latch_cont_on_n or clr_latch_once_o n_n for the homing process based on the n event ( home_event = b0000 ) . h oming with stopl and stopr stopl and stopr inputs can also be used as home_ref inputs . therefore , set stop_left_is_home = 1 re sp . stop_right_is_home = 1 (bit14 resp. bit15 of the reference_conf register 0x01) . this leads to a stop of the current ramp only after stopl or stopr is switching to active state and the home uncertainty region is crossed . the home uncertainty region is g iven by x_home and home_safety_margin . a ttention i n contrast to TMC4361old is possible to set x_home automatically with a write access to register 0x35. 10.4 repeating motion after r eaching xtarget usually , reaching xtarget in positioning mode finishes a veloc ity ramp. to repeat the current ramp with its specified parameters steadily set clr_pos_at_target to 1 (bit21 of the reference_conf register 0x01) . until velocity mode is chosen or clr_pos_at_target is set to 0 , xactual will be reset to 0 if xtarget is re ached ( xactual = xtarget ) . n ormally , t he falling slope to stop the ramp is performed with in each ramp cycle. t riggering further ramp s identical to the fir st one ( positioning mode only ) - set clr_pos_at_target = 1 - set xtarget . - now, xac t ual is set to 0 aut omatically if xtarget is reached . - a nother velocity ramp for reaching xtarget becomes active now.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 31 www.trinamic.com 10.5 circular movement many application are based on circular motion profiles. therefore, TMC4361 (but not TMC4361old!) offers a limitation of the range of xact ual with an automatic overflow processing. by setting x_range 0 (register 0x36, only writing access!) and activating circular_movement = 1 (bit22 of the reference_conf register 0x01) , xactual will be limited to: - x_range xactual x_range C 1. a tten tion by setting circular_movement to 1, xactual should be located inside of the defined range! the overflow will be processed automatically which means that if xactual reaches the most positive position ( x_range C 1) and the motion will proceed into posit ive direction, the next xactual value will be - x_range . the same is true when moving into negative direction, where ( x_range C 1) will be the position after - x_range . a ttention during positioning mode, the movement direction will be dependent on the short est path to the target position xtarget . for example, if xactual = 200, x_range = 300 and xtarget = - 200, the positioning ramp will find its way across the overflow position (299 ? - 300) (see figure 10 . 2 a)). due to definition of the limitation range, one revolution is only able to consist of an even number of microsteps. however, some application s demand other requirements. by setting circular_dec (0x7c) properly, these demands could be fulfilled. this register al lows a nearly free adjustable range of microsteps due to the fact that it represent one digit and 31 decimal places for the number of microsteps per one revolution. with every completed revolution (a revolution is completed at the overflow), the circular_d ec value will be added to an internal accumulation register. if this register has an overflow at bit31, it will remain at the overflow of xactual for one step. e xample 1 one revolution consists of 401 microsteps. a definition of x_range = 200 will only pr ovide 400 microsteps per revolution ( - 200 xactual 199), whereas x_range = 201 will result in 402 microsteps per revolution ( - 201 xactual 200) by setting circular_dec = 0x80000000 (= 2 31 / 2 31 = 1) every revolution an overflow will be produced at the decimals accumulation register. this leads to a microstep count of 401 per revolution. e xample 2 one revolution consists of 400.5 microsteps. by setting circular_dec = 0x40000000 (= 2 30 / 2 31 = 0.5) every second revolution an overflow will be produce d at the decimals accumulation register. this leads to a microstep count of 400 every second revolution and 401 for the other half of the revolutions. on average, this leads to 400.5 microsteps per revolution. e xample 3 one revolution consists of 401.25 mi crosteps. by setting circular_dec = 0xa0000000 (= (2 31 + 2 29 ) / 2 31 = 1.25) every revolution an overflow will produced at the decimals accumulation register. furthermore, every fourth revolution an additional overflow will occur which leads to another wait ing step. this leads to a microstep count of 401 for three of four revolutions and 402 for the remaining fourth of all revolutions. on average, this leads to 401.25 microsteps per revolution. by passing the overflow position the internal rev_cnt (0x36, onl y reading access) will be increased by one revolution if xactual will changed from ( x_range C 1) to - x_range or decreased by one revolution if xactual will take the other direction. if circular_cnt_as_xlatch (bit27 of the general _conf register 0x00) is set to 1, the register 0x36 will not display the x_latch value. instead, the revolution counter rev_cnt could be read out at this register address.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 32 www.trinamic.com 10.5.1 blocking zones if circular movement is enabled ( x_range 0 and circular_movement = 1), virtual stops could be used to set blocking zones, if both virtual stops are enabled and set properly. then, the blocking zones reaches from virtual_stop_left to virtual_stop_right . during positioning, the path from xactual to xtarget will not lead through the blocking zone which could result in a longer path then the direct one. however, the chosen deceleration ramp will be initiated as soon as one of the limits is reached. this may result from the velocity mode or if the t arget is located in the blocking zone. h int to get out of the blocking zone, clear the virtual stop events and set a regular target position outside of the blocking zone. TMC4361 will initiate a ramp with the shortest way to the target. a) b) figure 10 . 2 circular movement ( x_range = 300) , the green arrow depicts the path which is chosen for positioning: a) shortest path selection b) consideration of blocking zones to match an incremental encode r in the same manner, select circular_enc_en = 1 ( see chapter 0 ) 0 2 9 9 - 3 0 0 2 0 0 - 2 0 0 l o n g p a t h s h o r t p a t h 0 2 9 9 - 3 0 0 2 0 0 - 2 0 0 l o n g p a t h ( b u t f r e e ) s h o r t p a t h ( b u t b l o c k e d ) v s t o p l = - 2 9 0 v s t o p r = 2 2 0 0 2 9 9 - 3 0 0 2 0 0 - 2 0 0 l o n g p a t h ( a n d b l o c k e d ) s h o r t p a t h v s t o p l = 1 4 0 v s t o p r = 7 0
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 33 www.trinamic.com 10.6 target reached / p osition c omparison the target_reached pin 31 will forward the target_reached_flag. thus, if xactual = xtarget , target_reached is active. the p olarity could be configured via invert_pol_target_reached switch (bit16 of the general_conf register 0x00) . 10.6.1 connecting several target_reached pins (not implemented for TMC4361old) target_reached pin could be prepared the same way the intr pin could be conf igured for one intr signal transfer of several TMC4361 interrupt signals to the c. therefore, set intr _tr _pu_pd_en = 1 (bit 29 of the general_conf register 0x00) . per default then, the pin will work efficiently as wired - or due to the fact that during targ et_reached pin is inactive, the output is pulled weakly to the inactive pin level polarity. if the pin becomes active, it will pulled strongly towards the active polarity. connecting several pins at one signal line for the c will result in polarity change of the whole signal line if one of the TMC4361 target_r eached pins will be set active. by setting tr_as_wired_and = 1 (bit 31 of the general_conf register 0x00) , the signal line will act as wired - and . while the target position is not reached, the target_r eached pin will be pulled strongly towards the inactive polarity. during the active state, the pin will be pulled weakly at active polarity. that way, the whole signal line will be pulled to active state if all pins are forwarding the active polarity. 10.6.2 pos ition comparison besides comparing the internal position xactual or the external position enc_pos with an arbitrary value which could be set in pos_comp register 0x32 , TMC4361 provides the opportunity (in contrast to TMC4361old) to compare one of the posit ions wit h other register values. basic s ettings for position comparison (TMC4361 and TMC4361old) - choose a pos_comp value. the position compare register provides 32 bits. - choose a compare parameter by setting pos_comp_source (bit25 of the reference _conf re gister 0x01): ? set pos_comp_source = 1 for enc_pos. ? set pos_comp_source = 0 for xactual . the position compare process is permanently active. the stored pos_comp position is compared with xactual resp . enc_pos automatically. if pos_comp = xactual / enc_p os the status flag pos_comp_reached_f becomes set and the pos_comp_reached event becomes released, provided that switching to active state is done first. - additional, the output target_reached can be used to report the state of position comparison instead of the target reached status. therefore, set pos_comp_output = b11 (bit24:23 of the reference _conf register 0x01). further compare options (not implemented for TMC4361old) besides comparing xactual / enc_pos with pos_comp , it is also possible to compar e one of the positions with x_home or x_latch / enc_latch . this will be controlled by setting modified_pos_compare (bit29:28 of the reference _conf register 0x01) . finally, TMC4361 provides also the opportunity to compare the revolution counter rev_cnt wit h pos_comp . however, only the selected compare pair will generate the pos_comp_reached_f lag and the corresponding event. following pairs could be chosen for this flag generation: pos_comp_source: 0 1 modified_pos_compare 00 xactual vs. pos_com p enc_pos vs. pos_comp 01 xactual vs. x_home enc_pos vs. x_home 10 xactual vs. x_latch enc_pos vs. x _latch 11 rev_cnt vs. pos_comp enc_pos vs. enc _latch h int because it is possible that enc_pos will miss a defined microstep due to a coarse encod er resolution, pos_comp_reached _f will be also released if enc_pos will only pass its compare position.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 34 www.trinamic.com 11 ramp timing & synchroniz ation the TMC4361 provides various possibilities for ramp timing. usually, every external register change via an spi input is assigned immediately to the internal registers. with a proper start configuration of the TMC4361, ramp sequences without any intervening in between can be programmed. three stages of ramp start complexity are available. first, the distinct ramp start whose triggers and consequences will be explained first . two extensions are based on the start signal generation which could be used individually or combined. on the one hand, a complete shadow motion register set could be loaded in the current m otion registers to start the next ramp with an altered motion profile. on the other hand, different target positions could be predefined which will be activated successively with opportunit ies of a cyclic pipeline and/or pipelining of different p arameters . additional ly, a further start state busy could be assigned to synchronize several motion controllers for one start event. this part differs seriously from TMC4361old. please refer for the TMC4361old manual for the synchronization possibilit ies of this chip. p ins and r egisters : s ynchronization pin names type remarks start input, o utput , inout external start input to get a start signal or external start output to indicate an internal start event. register name register address remarks sta rt_conf 0x02 rw the c onfiguration register of the synchronization unit synchro_set 0x64 w synchronization set for closed loop considerations start_out_add 0x11 rw additional active output length of external start signal start_delay 0x13 rw delay time b etween start trigger and signal x_pipe07 0x380x3f rw target positions pipeline sh_reg013 0x400x4d rw alternative motion profile sets 11.1 start s ignal generation a ramp can be initiated using an internal or an external start trigger for the start signal generation . note that a start trigger is not the start signal itself but the transition slope to the active start state. now, for ramp start configuration consider the following steps: 1. choose internal or external start trigger(s) . 2. adjust the timing of the start signal after a start trigger has been recognized. 3. enable start signal processing . 11.1.1 starting a ramp via an internal start t rigger there are different triggers available for an internal start signal. these triggers are assigned by the trigger_events sw itches (bits 5 8) of the start_conf register 0x02 . every bit of trigger_event can be selected separately. thus, more than one signal can trigger a start event. trigger_events (8 : 5) description b00 b trigger_events (0) = 0 for internal start trigger only. the start pin as output . (if this bit is set to 1, an external trigger is chosen and the start pin is used as input ) b b b 11.1.2 starting a ramp via an external s tart t rigger there is one specific bit that has to be set for using an external trigger: trigger_events (8 : 5) description b trigger_events (0) = 1 for an external start trigger. then, the start pin is assigned as input. d efining the active v oltage level and the length of the start pin
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 35 www.trinamic.com the active voltage level of the start pin is defi ned by pol_start_signal (bit9 of start_conf register 0x02) . e xample s 1. set pol_start_signal = 0 a nd trigger_events (0) = 1 now, the voltage level transition from high to low triggers a start signal . the signal is further processed by the synchronization unit . 2. set pol_start_signal = 1 and trigger_events (0) = 0 now, start is used as output forwarding internal start signals with a high active level. h int per default, the active start signal last for one clock cycle. to extend the length of the active start outp ut, set the start_out_add register 0x11 appropriately. the value is given in clock cycles. a ttention external start signals should be filtered. 11.1.3 enabling delayed value transfer: start_en s ettings to enable a start signal considerations for specific r amp parameters it is necessary to set start_en (bit4:0 of the start_conf register 0x02) . a start signal can be used in different ways: start_en (4 : 0 ) description bxx xtarget is altered only after a start signal. b vmax is altered only after a start signal. bxx rampmode is altered only after a start signal. bx gear_ratio is altered only after a start signal. b 11.1.4 adjus tments related to start signal t iming and prioritiz ing every start switch can be enabled and disabled separately. in case an enable switch is set low, the particular register is changed immediately if the register is assigned by an spi datagram. using enable switches allows for setting specific points in t ime for altering register values. thus, the assignment of spi requests to the registers xtarget , vmax , ramp_mode , and gear_ratio could be uncoupled from the spi transfer itself. the assignment can be combined with trigger events which are related to the in ternal start signal generation. start_delay C setting a delay time for the start signal after a trigger for delaying an immediate ramp start , set start_delay register 0x13 to a reasonable value [clock cycles] . then, the chosen start_delay value defines t he time interval between the recognition of the chosen start trigger(s) and the internal start signal generation. for s witching off an ongoing start delay countdown set trigger_events = b00 00. immediate_start_in C prioritizing the external start signal for prioritizing the external start signal opposed to all other triggers set immediate_start_in = 1 (bit10 of start_conf register 0x02) . th us , an external start is executed immediately after its recognition independently from a given start_delay time, an a ctive timer, or other triggers. a ttention if an external start trigger is not used and the start pin is also not used for communication with an external device, connect it to gnd and select pol_start_signal = 1. alternatively, connect start to v io supply and set pol_start_signal = 0.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 36 www.trinamic.com 11.1.5 examples for ramp timing the following three examples depict spi datagrams, internal and external signal levels, corresponding velocity ramps, and additional explanations. spi data is transferred inte rnally at the end of eac h datagram. e xample 1 parameter setting description rampmode b 101 the velocity value change is executed immediately. the new xtarget value is assigned after target_reached has been set and start_delay has been elapsed. a new ramp does not start at the en d of the second ramp because there is no new xtarget value assigned. start is used as output. the internal start signal is forwarded with a step length of ( start_out_add + 1) clock cycles. this way, external devices could be synchronized. start_en b 0 00 01 trigger_events b 0010 start_delay >0 start_out_add >0 pol_start_signal 1 figure 11 . 1 start e xample 1 e xample 2 param e ter setting description rampmode b 001 the vel ocity value and ramp mode value change will be executed after the first start signal. because of the new ramp mode positioning mode and s - shaped ramps are activated and the ramp stops at target position. due to a further target request, the ramp starts aga in. the active start output signal lasts only one clock cycle. start_en b00 111 trigger_events b 0110 start_delay >0 start_out_add 0 pol_start_signal 0 s p i x t a r g e t = 2 0 0 0 v m a x = 2 0 0 0 v ( t ) 2 0 0 0 1 0 0 0 t a r g e t _ r e a c h e d v m a x _ r e a c h e d i n t e r n a l s t a r t s i g n a l s t a r t i n t e r n a l s t a r t t i m e r t s t a r t _ d e l a y s t a r t _ d e l a y s t a r t _ o u t _ a d d s t a r t _ o u t _ a d d t r i g g e r e v e n t t r i g g e r e v e n t x a c t u a l = 1 8 0 0 x a c t u a l = 2 0 0 0
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 37 www.trinamic.com figure 11 . 2 sta rt e xample 2 e xample 3 for this example start signal triggers have been prioritized due to the use of start timing via a start_delay setting and due to the setting immediate_start_in = 1. param e ter setting description rampmode b xactual = posco mp the start timer is activated and the external start signal in between is ignored. the second start event is triggered due to the external start signal. the poscomp_reached event is ignored. the third start timer process is disrupted by the external st art signal which is forced to be executed immediately due to the setting immediate_start_in = 1. start_en b00 trigger_events b immediate_start_in 0 start_delay >0 pol_start_signal 1 figure 11 . 3 start e xample 3 s p i v ( t ) 2 0 0 0 1 0 0 0 t a r g e t _ r e a c h e d v m a x _ r e a c h e d i n t e r n a l s t a r t s i g n a l s t a r t i n t e r n a l s t a r t t i m e r t s t a r t _ d e l a y t r i g g e r e v e n t r a m p m o d e = 1 1 0 v m a x = 1 0 0 0 x t a r g e t = 2 0 0 0 x t a r g e t = 2 0 0 0 t r i g g e r e v e n t t r i g g e r e v e n t v m a x = 2 2 5 0 s t a r t _ d e l a y x a c t u a l = 2 0 0 0 s p i v m a x = - 1 0 0 0 v ( t ) 1 0 0 0 p o s c o m p _ r e a c h e d i n t e r n a l s t a r t s i g n a l s t a r t i n t e r n a l s t a r t t i m e r t s t a r t _ d e l a y t r i g g e r e v e n t x a c t u a l = p o s c o m p - 1 0 0 0 v m a x = 1 0 0 0 s t a r t _ d e l a y t r i g g e r e v e n t v m a x = 2 5 0 v m a x = - 2 5 0 i m m e d i a t e _ s t a r t _ i n = 1 i g n o r e d t r i g g e r e v e n t d u e t o o n g o i n g s t a r t t i m e r t r i g g e r e v e n t t r i g g e r e v e n t x a c t u a l = p o s c o m p i g n o r e d t r i g g e r e v e n t d u e t o o n g o i n g s t a r t t i m e r
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 38 www.trinamic.com 11.2 shadow register set some application s requires a complete new ramp parameter set for a specific ramp situation resp. point in time. this could be achieved by setting start_en (4) = 1. it is also p ossible to write back the current motion profile into the shadow motion register set by setting cyclic_shadow_re s g = 1 (bit18 of start_conf register 0x02) . further on, f our different options for shadow register assignment are available by setting shadow_op tion appropriately (bis17:16 of start_conf register 0x02) : s hadow o ption 1: s et shadow _ option = b 00 for single - level shadow registe rs every relevant motion parameter will be altered at the next internal start signal. figure 11 . 4 single - level shadow register option s hadow o ption 2: s et shadow _ option = b 01 for a double - stage shadow registe r pipeline suitable fo r s - shaped ramps seven relevant motion parameter for s - shaped ramps will be altered at the next internal start signal. the register are arranged to a double - stage pipeline. if cyclic shadow registers are used, the current value will be stored in the second stage with the next start signal, e.g. 0x28 ( amax ) will be written back to 0x48 ( sh_reg8 ) . the other ramp registers remain unaltered. figure 11 . 5 double - stage shadow register option 1 2 0 r a m p m o d e 2 4 v m a x 2 5 v s t a r t 2 6 v s t o p 2 7 v b r e a k 2 8 a m a x 2 9 d m a x 2 a a s t a r t 2 b d f i n a l 2 d b o w 1 2 e b o w 2 2 f b o w 3 3 0 b o w 4 4 c s h _ r e g 1 2 4 0 s h _ r e g 0 4 6 s h _ r e g 6 4 7 s h _ r e g 7 4 5 s h _ r e g 5 4 1 s h _ r e g 1 4 2 s h _ r e g 2 4 3 s h _ r e g 3 4 4 s h _ r e g 4 4 8 s h _ r e g 8 4 9 s h _ r e g 9 4 a s h _ r e g 1 0 4 b s h _ r e g 1 1 x x x x x x r e g i s t e r a d d r e s s r e g i s t e r n a m e c y c l i c _ s h a d o w _ r e g = 0 c a p t i o n c y c l i c _ s h a d o w _ r e g = 1 2 0 r a m p m o d e 2 4 v m a x 2 5 v s t a r t 2 6 v s t o p 2 7 v b r e a k 2 8 a m a x 2 9 d m a x 2 a a s t a r t 2 b d f i n a l 2 d b o w 1 2 e b o w 2 2 f b o w 3 3 0 b o w 4 4 c 4 0 4 6 4 7 4 5 4 1 4 2 4 3 4 4 4 8 4 9 4 a 4 b s h _ r e g 1 2 s h _ r e g 0 s h _ r e g 6 s h _ r e g 7 s h _ r e g 5 s h _ r e g 1 s h _ r e g 2 s h _ r e g 3 s h _ r e g 4 s h _ r e g 8 s h _ r e g 9 s h _ r e g 1 0 s h _ r e g 1 1 4 0 4 6 4 5 4 1 4 2 4 3 4 4 x x x x x x r e g i s t e r a d d r e s s r e g i s t e r n a m e s t a r t _ e n ( 4 ) = 1 c a p t i o n c y c l i c _ s h a d o w _ r e g = 1 s h _ r e g 0 s h _ r e g 6 s h _ r e g 5 s h _ r e g 1 s h _ r e g 2 s h _ r e g 3 s h _ r e g 4 2 0 r a m p m o d e 2 4 v m a x 2 5 v s t a r t 2 6 v s t o p 2 7 v b r e a k 2 8 a m a x 2 9 d m a x 2 a a s t a r t 2 b d f i n a l 2 d b o w 1 2 e b o w 2 2 f b o w 3 3 0 b o w 4 4 7 4 8 4 9 4 a 4 b s h _ r e g 1 2 s h _ r e g 7 s h _ r e g 8 s h _ r e g 9 s h _ r e g 1 0 s h _ r e g 1 1 4 c s h _ r e g 1 3 4 d
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 39 www.trinamic.com s hadow o ption 3: s et shadow _ option = b 10 for a double - stage shadow registe r pipeline suitable fo r t rape zoidal ramps (vstart included ) seven relevant motion parameter for trapezoidal shaped ramps will be altered at the next internal start signal. the register are arranged to a double - stage pipeline. if cyclic shadow registers are used, the current value will be stored in the second stage with the next start signal, e.g. 0x27 ( vbreak ) will be written back to 0x4c ( sh_reg12 ). the other ramp registers remain unaltered . figure 11 . 6 double - stage shadow register o ption 2 s hadow o ption 4: s et shadow _ option = b 11 for a double - stage shadow registe r pipeline suitable fo r t rapezoidal ramps (vstop included ) seven relevant motion parameter for trapezoidal shaped ramps will be altered at the next internal start signa l. the register are arranged to a double - stage pipeline. if cyclic shadow registers are used, the current value will be stored in the second stage with the next start signal, e.g. 0x2a ( astart ) will be written back to 0x4a ( sh_reg1 0 ). the other ramp regist ers remain unaltered. figure 1 1 . 7 double - stage shadow register option 3 4 0 4 6 4 5 4 1 4 2 4 3 4 4 x x x x x x r e g i s t e r a d d r e s s r e g i s t e r n a m e s t a r t _ e n ( 4 ) = 1 c a p t i o n c y c l i c _ s h a d o w _ r e g = 1 s h _ r e g 0 s h _ r e g 6 s h _ r e g 5 s h _ r e g 1 s h _ r e g 2 s h _ r e g 3 s h _ r e g 4 2 0 r a m p m o d e 2 4 v m a x 2 5 v s t a r t 2 6 v s t o p 2 7 v b r e a k 2 8 a m a x 2 9 d m a x 2 a a s t a r t 2 b d f i n a l 2 d b o w 1 2 e b o w 2 2 f b o w 3 3 0 b o w 4 4 7 4 8 4 9 4 a 4 b s h _ r e g 1 2 s h _ r e g 7 s h _ r e g 8 s h _ r e g 9 s h _ r e g 1 0 s h _ r e g 1 1 4 c s h _ r e g 1 3 4 d 4 0 4 6 4 5 4 1 4 2 4 3 4 4 x x x x x x r e g i s t e r a d d r e s s r e g i s t e r n a m e s t a r t _ e n ( 4 ) = 1 c a p t i o n c y c l i c _ s h a d o w _ r e g = 1 s h _ r e g 0 s h _ r e g 6 s h _ r e g 5 s h _ r e g 1 s h _ r e g 2 s h _ r e g 3 s h _ r e g 4 2 0 r a m p m o d e 2 4 v m a x 2 5 v s t a r t 2 6 v s t o p 2 7 v b r e a k 2 8 a m a x 2 9 d m a x 2 a a s t a r t 2 b d f i n a l 2 d b o w 1 2 e b o w 2 2 f b o w 3 3 0 b o w 4 4 7 4 8 4 9 4 a 4 b s h _ r e g 1 2 s h _ r e g 7 s h _ r e g 8 s h _ r e g 9 s h _ r e g 1 0 s h _ r e g 1 1 4 c s h _ r e g 1 3 4 d
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 40 www.trinamic.com a ttention the value of ramp parameters which are not affected by shadow register due to the selected shadow option will persist if th e register will not be changed due to a spi write access . up to fifteen internal start signals c ould be skipped before the shadow regis ter transfer should be executed. therefore, shadow_miss_cnt ( bit23:20 of start_conf register 0x02) has to be set accordin gly. figure 11 . 8 depicts an example for the usage of shadow_miss_cnt where the shadow register transfer is illustrated by an internal signal sh_reg_transfer . the current miss counter could be read out at register address start_con f (2 3 : 20): figure 11 . 8 usage of the shadow_miss_cnt parameter to delay the shadow register transfer for several internal start signals h int if no cyclic values are enabled, the first stage of the pipelin e will persist until its values will be changed. thus, not altering the shadow registers will result in concurrence of the values of one pipeline if sufficient start signals have been occurred. for example, shadow_option = b01, cyclic_shadow_reg = 0, and shadow_miss_cnt = 0, will result in bow1 = sh_reg3 = sh_reg8 after two start signals and if every of these register values have not been altered so far. a ttention calculation to transfer the requested shadow bow values into internal structures will requir e at most (320 ? f clk ) [sec] . thus, it have to be assured that the point in time , when the values of the shadow registers will be transferred to valid ramp parameters , should be delayed after the last shadow bow assignment for this time sp an . following seq uence could be adopted for shadow register assignment with a followed shadow register transfer (example: shadow_option = b01) 1. set sh_reg0 , sh_reg1 , sh_reg2 (shadow register for vmax , amax , dmax ) 2. set sh_reg3 , sh_reg4 , sh_reg5 , sh_reg 6 (shadow registe r for bow1 4 ) 3. wait for 320 ? f clk 4. shadow register transfer could be initiated a ttention it is strongly recommended that the values of the s hadow ramp parameters should be only transferred during standstill of the current ramp ( vactual = 0), especial ly if the ramp_mode will be changed. anyhow, if the transfer should happen during motion, vactual have to be constant for all ramp types . further on, it have to be assured that vactual will remain constant for a definite delay t shadow_transfer before any f urther vmax or xtarget changes will be assigned if s - shaped ramps are performed due to recalculation reasons: ? ?????? _ ???????? > max ? ( ??? 3 [ ?? ? 3 ] ; ??? 4 [ ?? ? 3 ] ) ? ???? [ ??? ] 56 ? ??? 3 [ ?? ? 3 ] if positioning mode is selected, xtarget have to be set accordingly to maintain a constant vactual value. it is also required that vmax and it shadow counterpart have to be equal to avoid vactual alteration during t shadow_transfer . s p i s h a d o w _ m i s s _ c n t = 0 i n t e r n a l s t a r t s i g n a l s h a d o w _ m i s s _ c n t = 5 s h a d o w _ m i s s _ c n t = 2 1 2 3 4 5 0 1 2 0 1 2 0 1 0 c u r r e n t _ m i s s _ c n t s h _ r e g _ t r a n s f e r
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 41 www.trinamic.com 11.3 target pipeline the TMC4361 provides a target pipeline for sequencing subordinate targets during the drive. this way, a complex target structure can be easily arranged. thus, pipeline_en = b0001 have to be set (bit15:12 of start_conf register 0x02) . now, the value in x_pipe0 becomes transferred to xtarget at the next internal start signal. the complete a target pipeline x_pipe0 x_pipe7 will be shifted fo rward step by step following the condition x_pipe n = x_pipe n+1 . this f lexible target pipeline provides up to eight additional target positions which become transferred at the next specific start signal . the actual valid target position is written back to x_pipe x , where x is equal to the bit position of xpipe_rewrite_reg (bit31:24 of start_conf register 0x02) . more precisely, if xpipe_rewrite_reg = b 00010000, x_pipe4 = xactual at the next internal start signal. if xpipe_rewrite_reg = b 00000000, xtarget w ill not written back to any x_pipe n register. if multiple bits are set, xtarget will written back to each of the selected x_pipe n registers. figure 11 . 9 flexible target pipeline 11.4 p artitioned t arget pipeline the TMC4361 pipeline (registers 0x380x3f) could be split into up to four segments to provide a pipeline opportunity for other parameters whose defined parameter value change could be important for a continuous ramp motion and/or for reduced overhead sync hronizing several motion controllers. besides the introduced pipelining of the target register, it is also possible to pipeline the pos_comp (0x32) , the gear_ratio (0x12) , and the general_conf (0x00) registers. t he pos_comp could be used to initiate a star t signal generation during motion. thus, it could be useful to pipeline this parameter to avoid the dependence on the spi transfer speed. for instance, if the distance between two pos_comp values is very close and the current velocity is high enough to mis s the second value before the spi transfer is finished, it would be better to change pos_comp immediately after the start signal. the same could be true for gear_ratio which define s the step response on incoming step impulses. some applications require ver y quick gear factor alteration of the slave controller whose immediate change at start signal appearance could be very useful in contrast to the alteration due to a spi transfer. likewise, it is yet essential to change general configuration parameters at a defined point in time. a suitable application could be the defined transfer from a direct external control ( sd_in_mode = b01) to an internal ramp ( sd_in_mode = b00) or vice versa because the master/slave relationship will be interchanged. thus, followin g pipeline options are available which could be adjusted freely: pipeline _en (3 : 0 ) description bx xtarget is enabled. b pos_comp is enabled. bx gear_ratio is enabled. b general_con f is enabled. 3 7 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 x t a r g e t x _ p i p e 0 x p i p e _ r e w r i t e _ r e g ( 0 ) = ' 1 ' x x x x x x r e g i s t e r a d d r e s s r e g i s t e r n a m e c a p t i o n p i p e l i n e _ e n = b 0 0 0 1 p i p e l i n e _ e n = b 0 0 0 1 x _ p i p e _ r e w r i t e _ r e g 0 x p i p e _ r e w r i t e _ r e g ( 1 ) = ' 1 ' x p i p e _ r e w r i t e _ r e g ( 2 ) = ' 1 ' x p i p e _ r e w r i t e _ r e g ( 3 ) = ' 1 ' x p i p e _ r e w r i t e _ r e g ( 4 ) = ' 1 ' x p i p e _ r e w r i t e _ r e g ( 5 ) = ' 1 ' x p i p e _ r e w r i t e _ r e g ( 6 ) = ' 1 ' x p i p e _ r e w r i t e _ r e g ( 7 ) = ' 1 '
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 42 www.trinamic.com 11.4.1 pipeline sections as stated before, the pipeline_en switches could be set freely. as a result the number of pipelines range from 0 to 4. this again has an impact of the pipeline depth whose variety ranges between eigth - stage, four - stage, th ree - stage and double - stage pipelines behind the target registers. in the following table the arrangement and depth of the pipeline is allocated as regards pipeline setup. the transfer combination is also depicted which illustrates from which pipeline regis ters (x_pipe07) the final target registers ( xtarget , pos_comp , gear_ratio , general_conf ) are feed. pipeline _en (3 : 0 ) arrangement final transfer register xtarget pos_comp gear_ratio general_conf b0000 b0001 x_pipe0 - - - b0010 x_pipe0 - - b0100 x_pipe0 - b1000 x_pipe0 b0011 x_pipe0 x_pipe 4 - - b0101 x_pipe0 - x_pipe 4 - b1001 x_pipe0 - - x_pipe 4 b0110 x_pipe0 x_pipe 4 - b1010 x_pipe0 - x_pipe 4 b110 x_pipe0 x_pipe 4 b0111 x_pipe0 x_pipe 3 x_pipe 6 - b1011 x_pipe0 x_pipe 3 - x_pipe 6 b1101 x_pipe0 - x_pipe 3 x_pipe 6 b1110 x_pipe0 x_pipe 3 x_pipe 6 b1111 x_pipe 0 x_pipe 2 x_pipe 4 x_pipe 6 in the followin g several examples are depicted. a) b) figure 11 . 10 one pipeline with a) 8 stages and b) 6 stages behind the target register 3 2 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 p o s _ c o m p x _ p i p e 0 p i p l i n e _ e n = b 0 0 1 0 x p i p e _ r e w r i t e _ r e g = b 1 0 0 0 0 0 0 0 1 2 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 g e a r _ r a t i o x _ p i p e 0 x _ p i p e _ r e w r i t e _ r e g ( 7 ) = b 0 0 1 0 0 0 0 0 p i p l i n e _ e n = b 0 1 0 0 x p i p e _ r e w r i t e _ r e g = b 0 0 1 0 0 0 0 0
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 43 www.trinamic.com a) b) figure 11 . 11 two pipelines with a) each 4 stages and b) 3/2 stages behind the target registers a) b) figure 11 . 12 a) two pipelines with 3 stages and one pipeline with 2 stages b) two pipelines with 2 stages and one pipeline with 2 stages, but without writing data back a) b) figure 11 . 13 four pipelines with 2 stages with a) and without b) writing back data 3 2 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 p o s _ c o m p x _ p i p e 0 3 7 x t a r g e t p i p l i n e _ e n = b 0 0 1 1 x p i p e _ r e w r i t e _ r e g = b 1 0 0 0 1 0 0 0 1 0 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 g e n e r a l _ c o n f x _ p i p e 0 p i p l i n e _ e n = b 1 1 0 0 x p i p e _ r e w r i t e _ r e g = b 0 0 1 0 0 1 0 0 1 2 g e a r _ r a t i o 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 x _ p i p e 0 3 7 x t a r g e t p i p l i n e _ e n = b 1 1 0 1 x p i p e _ r e w r i t e _ r e g = b 1 0 1 0 0 1 0 0 1 0 g e n e r a l _ c o n f 1 2 g e a r _ r a t i o 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 x _ p i p e 0 3 7 x t a r g e t p i p l i n e _ e n = b 0 1 1 1 x p i p e _ r e w r i t e _ r e g = b 1 0 0 0 0 0 1 0 1 2 g e a r _ r a t i o 3 2 p o s _ c o m p 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 x _ p i p e 0 3 7 x t a r g e t p i p l i n e _ e n = b 1 1 1 1 x p i p e _ r e w r i t e _ r e g = b 1 0 1 0 1 0 1 0 1 0 g e n e r a l _ c o n f 1 2 g e a r _ r a t i o 3 2 p o s _ c o m p 3 8 3 9 x _ p i p e 1 3 a x _ p i p e 2 3 b x _ p i p e 3 3 c x _ p i p e 4 3 d x _ p i p e 5 3 e x _ p i p e 6 3 f x _ p i p e 7 x _ p i p e 0 3 7 x t a r g e t p i p l i n e _ e n = b 1 1 1 1 x p i p e _ r e w r i t e _ r e g = b 0 0 0 0 0 0 0 0 1 0 g e n e r a l _ c o n f 1 2 g e a r _ r a t i o 3 2 p o s _ c o m p
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 44 www.trinamic.com h int as it have be en depicted, the pipeline register which will get the current data of any of the target registers ( xtarget , pos_comp , gear_ratio , general_conf ) will be adjusted also by the xpipe_rewrite_reg register . by setting one of these bits to 1, the appropriate regi ster will get the data of the particular target register. the assignment is dependent on the pipeline_en settings. the written back order will be always prior to the pipelining mechanism for x_pipe0 x_pipe7 . therefore, shorter cyclic pipelines than default ones are always possible. 11.5 synchronizing several motion controllers coming soon a ttention if the start pin is connected with start pins of other TMC4361 devices, a series resistor (e.g. 220 ) should be connected between the devices to limit the short cir cuit current flowing if the configuration of the start signals will result in different voltage levels at the start pins of the different devices. a possible short circuit must last only for a short time .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 45 www.trinamic.com 12 serial data output the TMC4361 provides a n spi i nterface for initialization and conf iguration of the motor driver (additional to the step/dir output) before and during motor motion. furthermore, it is possible to control triniamic stepper drivers during spi motor drive. the spi interface is used for pri ncipal tasks: - t wo current values of the integrated sine wave look - up table can be transferred at a time to the driver chip in order to energize the motor coils. this is done within each spi datagra m. a series of current values is transferred to move the mo tor. values of the mslut (microstep sine wave look - up table) are adjusted using velocity ramp dependent scale values. this way, maximum amplitude current values are aligned to the requirements of certain velocity slopes. - t he TMC4361 integrates an adjustab le cover register for configuration purposes. this way, triniamic motor driver chips and third parties chips can be ad justed with only little effort. p ins and r egisters : spi to m otor d river pin names type remarks nscsdrv _sdo output chip select output to m otor driver, low active sckdrv _nsdo output serial clock output to motor driver sdodrv _sclk ino ut as output serial data output to motor driver sdidrv _nsclk input serial data input from motor driver stdby_clk output c lock output, standby output , or c hop s ync clock output register name register address remarks general_conf 0x00 rw bit 14 ? 13 , bit 19, bit 20 , bit28 reference_conf 0x01 rw bit 26, bit 27 , bit 30 spiout_conf 0x04 rw configuration register for spi output communication step_conf 0x0a rw micro steps/fullstep, fullstep/revolution, and motor status bit event selection dac_addr 0x1d rw spi addresses/commands which are put in front of the dac values: coila: dac_addr (15 : 0) ; coilb: dac_addr ( 31:16 ) spi_switch_vel 0x1f rw velocity at which automatic cover datagram will be sent chopsync_div chopper clock divider (bit 11 ? 0) fs_vel 0x60 w velocity at which fullstep drive will be enabled cover_low 0x6c w lower 32 bit of the cover register (c to motor driver) cover_high 0x6d w upper 32 bit of the co ver register (c to motor driver) cover_drv_low 0x6e r lower 32 bit of the cover register (motor driver to c) cover_drv_high 0x6f r upper 32 bit of the cover register (motor driver to c) register name register address remarks current_conf 0x05 rw cur rent scaling configuration scale_values 0x06 rw current scaling values stdby_delay 0x15 rw delay time after standby mode is valid freewheel_delay 0x16 rw delay time after freewheeling is valid vdrv_scale_limit 0x17 rw velocity setting for changing the drive scale value up_scale_delay 0x18 rw increment delay to a higher scaling value; 24 bit hold_scale_delay 0x19 rw decrement delay to the hold scaling value; 24 bit drv_scale_delay 0x1a rw decrement delay to the drive scaling value boost_time 0x1b rw delay time after ramp start when boost scaling is valid scale_param 0x7c r actual scaling parameter; 8 bit currenta currentb 0x7a r actual current values of the mslut : sin (coil a) and sin90_120 (coil b); each 9 bit currenta_spi currentb_spi 0x7b r ac tual scaled current values of the mslut : sin (coil a) and sin90_120 (coil b); each 9 bit register name register address remarks mslut registers 0x707 8 w mslut values definitions mscnt 0x79 r current microstep position of the mslut start_sin start_sin 90_120 dac_offset 0x7e rw sine start value of the mslut (bit 7 ? 0) cosine start value of the mslut (bit 23 ? 16) offset value for dac output values (bit 31 ? 24)
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 46 www.trinamic.com h int for a good start with a trinamic motor driver, setup spiout_conf register 0x04 properly. t hus, the TMC4361 offers presets for current transfer and automatic configuration routines if the correct driver is selected. status bits of tmc motor drivers are also transmitted to the status register of the motion controller. 12.1 sine wave look - up table tmc 4361 provides a programmable look - up table for storing the microstep current wave. as a default, the tables are pre - programmed with a sine wave, which is a good starting point for most stepper motors. reprogramming the table to a motor specific wave allows drastically improved microstepping especially with low - cost motors. in order to minimize required memory and the amount of data to be programmed, only a quarter of the wave becomes stored. the internal microstep table maps the microstep wave from 0 to 90 . it becomes symmetrically extended to 360. when reading out the table the 10 - bit microstep counter mscnt addresses the fully extended wave table. the table is stored in an incremental fashion, using each one bit per entry. therefore only 256 bits ( ofs00 to ofs255 ) are required to store the quarter wave. these bits are mapped to eight 32 bit registers. each ofs bit controls the addition of an inclination wx or wx +1 when advancing one step in the table. as the wave can have a higher inclination than 1, th e base inclinations wx can be programmed to - 1, 0, 1, or 2 using up to four flexible programmable segments within the quarter wave. this way, even a negative inclination can be realized. the four inclination segments are controlled by the position register s x1 to x3 . when modifying the wave, care must be taken to ensure a smooth and symmetrical zero transition when the quarter wave becomes expanded to a full wave. the maximum resulting swing of the wave should be adjusted to a range of - 248 to 248, in orde r to give the best possible resolution while leaving headroom for the hysteresis based chopper to add an offset. figure 12 . 1 lut programming example when the microstep sequence r advances within the table, it calculates the actual current values for the motor coils with each microstep and stores them to the registers currenta and currentb . however the incremental coding requires an absolute initialization, especially when the mic rostep table becomes modified. therefore, currenta and currentb become initialized whenever mscnt passes zero. t wo registers control the starting values of the tables : - as the starting value at zero is not necessarily 0 (it might be 1 or 2), it can be prog rammed into the starting point register start_sin . - in the same way, the start of the second wave for the second motor coil needs to be stored in start_sin90_120 . this register stores the resulting table entry for a phase shift of 90 for 2 - phase stepper m otors. m s c n t y 2 5 6 2 5 6 2 4 8 - 2 4 8 5 1 2 7 6 8 0 0 x 1 x 3 x 2 w 0 : + 2 / + 3 w 1 : + 1 / + 2 w 2 : + 0 / + 1 w 3 : - 1 / + 0 l u t s t o r e s e n t r i e s 0 t o 2 5 5 2 5 5 s t a r t _ s i n s t a r t _ s i n 9 0 _ 1 2 0
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 47 www.trinamic.com 12.1.1 programming the incremental microstep table for understanding the background of the incremental coding of the microstep table, it is good to have an idea of the characteristics of the microstep wave. a microstep table for a two phase motor ha s certa in characteristics : 1. it is in principle a reverse characteristic of the motor pole behavior. 2. it is a smoothened wave to provide a smooth motor behavior. there are no jumps within the wave. 3. the phase shift between both phases is exactly 90, because this i s the optimum angle of the poles within the motor. 4. the zero transition is at 0. the curve is symmetrical within each quadrant (like a sine wave). 5. the slope of the wave is normally positive, but due to torque variations it can also be (slightly) negative. 6. but it must not be strictly monotonic as the example in the previous chapter shows. considering these facts, it becomes clear that the wave table can be compressed. the incremental coding used in the TMC4361 uses a format which reduces the required infor mation per entry of the 8 bit by 256 entry wave table to slightly more than a single bit. i ncremental e ncoding the principle of incremental encoding just stores the difference between the actual and the next table entry. to have an absolute start value, t he first entry is directly stored ( start_sin ). for the ease of use, also the first entry of the shifted table for the second motor phase is stored ( start_sin_90_120 ). the TMC4361 provide s four inclination segments (0, 1, 2, and 3) with the base inclination s (w0, w1, w2, and w3) and the segment borders (0, x1, x2, x3, and 255). inclination segment base inclination segments 0 w0 0 x1 x1 x2 x2 x3 x3 255 table 12 . 1 inclination segments of t mc4361 e xplanatory notes and examples using a single bit per table entry allows any inclination between 0 and 1. e.g., a 0 - bit can mean do not add anything and a 1 - bit can mean add one . this allows describing a digital slope of 0 (all bits zero) to 45 (a ll bits one). it becomes clear, that higher inclinations are necessary. however, the inclination will not drastically change from point to point. therefore, the wave can be divided into up to four segments with different base inclinations. using a base i nclination of one, a 0 - bit means add one and a 1 - bit means add two . this way, a slope between 45 (all bits zero) and 77.5 is yielded (all bits one). figure 12 . 2 wave showing se gments with all possible base inclinations (highest inclination first) y 2 5 6 0 + 2 / + 3 + 1 / + 2 + 0 / + 1 - 1 / + 0 2 5 5 x 1 x 2 x 3 s e g m e n t u p p e r l i m i t s s e g m e n t l o w e r l i m i t s 0 s e g m e n t i n c l i n a t i o n w
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 48 www.trinamic.com h int the base inclinations can be set between - 1 (falling slope) and +2. this way, slopes between - 45 and 78.75 can be described. the default sine wave table in trinamic drivers uses one segment with a base inclination of 1 and one segment with a base inclination of 0. e xample c onsider the given co nditions : the microstep table for the standard sine wave begins with the eight entries (0 to 7) {0, 1, 3, 4, 6, 7, 9, 10 } etc. the maxi mum inclination in this area is 2 (1+2=3). the minimum inclination in these eight entries is 1. the start value is 0. advancing in the table, the first time the inclination becomes lower than +1 is from position 153 to position 154. both entries are ide ntical. the calculated value for position 256 (start of cosine wave) is 247. t herefore , the following settin gs need to be made : - set a starting value start_sin =0 matching sine wave entry 0. - set a base inclination range of w0 : +1 / +2 ( w0 =%10), valid fr om 0 to x1 . - calculate the differences between each two entries: {+1, +2, +1, +2, +1, +2, +1,} - set the microstep table entries ofsxx to 0 for the lower value (+1), 1 for the higher value (+2). thus, the first seven microstep table entries ofs00 to ofs06 ar e: {0, 1, 0, 1, 0, 1, 0 } - latest at position 153, the inclination must be lowered. use the next inclination range 1 with w1 : +0 / +1 ( w1 =%01). therefore, x1 becomes set to 153 in order to switch to the next inclination range. thus, starting from position 153, an offset ofsxx of 0 means add nothing, 1 means add +1. - start_sin90_120 becomes equal to the value at position 256, i.e. 247. - as the wave does not more have segments with different inclinations, the remaining inclination ranges w2 and w3 shall be set to the same value as w1, and x2 and x3 can be set to 255. this way, only two inclination segments are effective. o verview of example microstep number 0 1 2 3 4 5 6 7 153 154 desired table entry 0 1 3 4 6 7 9 10 200 200 difference to next entr y 1 2 1 2 1 2 1 0 required segment inclination +1 +1 +1 +1 +1 +1 +1 +0 offs bit entry 0 1 0 1 0 1 0 0
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 49 www.trinamic.com 12.2 spi output p arameters the TMC4361 provides spi output parameters to adjust a proper communication with the motor driver. set serial_enc_out_enable = 0 (bit24 of general_conf register 0x00) to enable the spi output communication. the TMC4361 generates the necessary spi output clock frequency and forwards it to the sckdrv_nsdo output pin. the low phase of the serial clock is set with spi_out_low_time (bit23:20 of spiout_conf register 0x04) , whereas spi_out_high_time (bit27:24 of spiout_conf register 0x04) sets the high phase. additionally, an spi_out_block_time (bit31:28 of spiout_conf register 0x04) can be set for a minimum time period where no new datagram will be sent after the last spi output datagram. during this inactive phase sckdrv_nsdo stays high. all three spi output parameters consist of 4 bit and represent a number of clock cycles. p ins which are affect ed by spi outp ut communication nscsdrv_sdo low active chip select signal sckdrv_nsdo spi output clock sdodrv_sclk used as output to transfer the datagram to the motor driver sdidrv_nsclk receives the response from the motor driver. the response is sampled during t he data transfer to the motor driver. m inimum and m ax imum t ime p eriod the minimum time period for all three parameters is 1/f clk . if an spi output parameter is set to 0 it becomes altered to 2 clock cycle s internally. a max imum time period of 15/f clk can be set for all three parameters. thus, spi clock frequency f spi_clk covers the following range: f clk /30 f spi_clk f clk /2. the timing of the spi output communication is illustrated in figure 12 . 3 . figure 12 . 3 spi output datagram timing (cdl C cover_data_length) cover_done at the end of a successful data transmission, the event cover_done becomes set. this indicates that the cover register data have b een sent to the motor driver and that received responses have been stored in the registers cover_drv_high (0x6e) and cover_drv_low (0x6f) . cover_drv _ high and cover_drv _ low form the cover response register. the event cover_done becomes also set after a suc cessful current datagram transmission. n s c s d r v _ s c l k s c k d r v _ n s d o s d o d r v _ s c l k s d i d r v _ n s c l k b i t c d l - 1 b i t c d l - 2 b i t 0 b i t 3 9 b i t 3 8 b i t 0 s p i _ o u t _ l o w _ t i m e / f c l k s p i _ o u t _ b l o c k _ t i m e / f c l k s p i _ o u t _ h i g h _ t i m e / f c l k s a m p l e p o i n t s
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 50 www.trinamic.com 64 bit spi cover register s for communication between c and driver the 64 bit spi cover register is separated in to two 32 bit registers - cover_high (0x6c) and cover_lo w (0x6d) . using the cover register s , an additi onal spi communication channel between microcontroller and motor driver is not needed. the total length of the cover register can be set by cover_data_length . if this parameter is set higher than 64, the cover register data length is still 64 bits at its m aximum. the lsb (last significant bit) of the whole cover register is located at cover_low (0). thus, if less than 33 bits are required for spi communication, only cover_low respectively a part of it will be transmitted (in accordance to cover_data_length ) . the cover register and the datagram structure are illustrated in figure 12 . 4 . every spi communication starts with the most significant bit ( msb ): - msb is cover_low ( cover_data_length - 1) if cover_data_length < 33 . - msb is cover _high ( cover_data_length - 33) if cover_data_length 33. h int similar to cover_low and cover_high , the motor driver response is divided in the registers cover_drv_low and cover_drv_high . the composition of the response cover register and the positioning o f the msb follow the same structure. figure 12 . 4 cover data register composition (cdl C cover_data_length) 12.3 automatic cover datagrams TMC4361 provides the opportunity to send a utomatically cover datagrams if a certain ramp velocity is reached. if automatic_cover is set to 1 the data in cover_high will be transferred if vactual passes spi_switch_vel to an absolute higher velocity. whereas, cover_low will be sent if vactual passes spi_switch_vel to absolute lower values. obviously, the spi slave should not have expect datagrams with more than 32 bits. 12.4 current datagrams TMC4361 uses the introduced internal microstep look - up table (mslut) for providing current data for the motor dri ver. with every step initialized by the ramp generator the mscnt value becomes increased or decreased, dependent on the ramp direction. the mscnt register 0x79 (readable value) contains the current microstep position of the sine value. accordingly, the cur rent values currenta (0x7a) and currentb (0x7b) are altered. in case the output configuration of the TMC4361 allows for automatic current transfer an updated current value leads to a new datagram transfer. this way, the motor driver always receives the l atest data. the length for current datagrams could be set automatically and the t mc4361 converts new values into the selected datagram format, usually divided in amplitude and polarity bit for tmc motor drivers . note that the tmc23x and tmc24x only forwa rd new current data if the upper five bits of one of the two 9 bit current values have changed. this is because tmc23x and tmc24x current data consist of four bit current values and one polarity bit for each coil. further on , tmc23x and tmc24x current data grams forward mixed decay bits. these bits can be set with mixed_decay (bit5:4 of spiout_conf register 0x04) . please refer to the tmc23x/tmc24x datasheets to get more information about setting mixed decay bits correctly. b i t 6 3 b i t 6 2 b i t 3 3 b i t 3 2 . . . b i t 3 1 b i t 3 0 b i t 1 b i t 0 . . . b i t 3 1 b i t 3 0 b i t 1 b i t 0 . . . c o v e r _ h i g h c o v e r _ l o w c o v e r r e g i s t e r b i t 3 1 b i t 3 0 b i t 1 b i t 0 . . . m s b i f c d l = 6 3 m s b i f c d l = 3 0 ( c o v e r _ h i g h n o t r e q u i r e d )
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 51 www.trinamic.com 12.5 tmc motor driver for connecting a tmc stepper motor driver proceed as follows: the TMC4361 is able to set the cove r register length automatically. therefore, set cover_data_length = 0 (bit19:13 of spiout_conf register 0x04) . now , the cover register length is set according to the chosen sp i_output_format setting (bit3:0 of spiout_conf register 0x04) . spi_output_format is the essential parameter for choosing predefined spi default settings for the particular tmc motor driver. tmc s tepper m otor d river and s ettings tmc motor driver spi_output _format 3 ? 0 automatic current datagram transfer cover register length cover_data_lengh =0 tmc23x b 1000 ? 12 tmc24x b 1001 ? 12 tmc26x/389 spi output for conf. only b 1010 b 1011 ? - 20 20 tmc21xx/51xx spi output for conf. only b 1101 b 1100 ? - 40 40 12.5.1 swit ching from steps to fullsteps TMC4361 provides switching to fullstep mode if the absolute velocity value vactual exceeds the parameter fs_vel , which is the minimum fullstep velocity. in case , e.g., the step/dir output is used, switching from microsteps to fullsteps can lead to a step rate which is 256 times lower than before, assumed that the highest microstep resolution is set. to indicate this microstep resolution change to the microcontroller, the event fs_active becomes released and thus the microcontr oller can adapt the motor driver configuration properly . h int for enabling fullstep drive set fs_en =1 (bit19 of general_conf register 0x00) . tmc260, tmc261, tmc262, tmc2660, tmc389 , tmc21 xx /51 xx : a utomatic f ullstep s witchover these advanced motor driver chips offer two interfaces for communication with the motion controller: spi and step/dir. the TMC4361 provides related data for both interfaces concurrently. decreasing the microstep resolution during a velocity ramp has to be done very carefully. for th e ease of use, the TMC4361 provides configuring tmc motor drivers automatically. spi output used for conf iguration and curren t datagrams for this configuration set spi_output_format = b 1010 (tmc26x/389) resp. b 110 1 ( tmc21xx/51xx ) . now, current values be come switched to fullstep values if | vactual | > fs_vel , the internal microstep position of the TMC4361 suits, and fs_en = 1 has been set before . consistently, a switchback from fullsteps to microsteps becomes executed if | vactual | < fs_vel . s tep /d ir interf ace used for moving the motor and spi output only used for configuration for this configuration set spi_output_format = b 1011 (tmc26x) resp. b1100 ( tmc21xx/51xx ) , fs_en = 1, and fs_sdout = 0. a ttention note that fs_sdout (bit20 of general_conf registe r 0x00) is only to be used if a motor driver does not provide switching between fullsteps and microsteps automatically . setting this bit to active state, automatic fullstep interchange will be disturbed. a continuous polling for spi datagrams is necessary to get status data from the drivers. therefore, set disable_polling = 0 ( bit6 of spiout_conf register 0x04) . by setting poll_block_mult (bit12: 7 of spiout_conf register 0x04) properly, the time between two consecutive polling datagrams becomes
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 52 www.trinamic.com extended to ( poll_block_time + 1) ? spi_out_block_time / f clk du ring polling . a high fullstep frequency requires a short spi datagram polling time. a ttention t he fullstep switch for the tmc26x and tmc389 requires a correct assignment of the read selection bits in th e driver registers. if these bits are not set to b 00 the transition to fullsteps cannot not be executed due to the fact that the TMC4361 does not receive any microstep data from the driver. if fullstep drive is requested and | vactual | > fs_vel , the motor driver (tmc26x or tmc21xx/51xx ) is polled to recognize the correct point in time to switch to full steps. this moment becomes reached when the microstep position of the motor driver equals a fullstep position. the same operation is carried out if fullstep drive has to be switched back to microstep drive. tmc 23 x and tmc24 x : a utomatic s witchover to f ullsteps set spi_output_format = b 1000 for tmc23x or spi_output_format = b 1001 for tmc24x motor drivers . now, current values become switched to fullstep valu es if | vactual | > fs_vel , the internal microstep position of the TMC4361 suits, and fs_en = 1 has been set before . consistently, a switchback from fullsteps to microsteps becomes executed in case | vactual | < fs_vel . c hanging the m icrostep r esolution by alt ering the microstep resolution from 256 ( mstep_per_fs = b 0000) to a lower value, an internal step results in more than one mslut step. if, e.g., the microstep resolution is set to 64 ( mstep_per_fs = b0010), the mscnt becomes in - /decreased by 4 for one in ternal step. accordingly, the passage through the mslut skips three current values for each internal step to match the new microstep resolution. 12.5.2 how to u se the c urrent scale parameter via spi o utput further automatic driver configuration for spi_output_for mat = b 1100 and spi_output_format = b 1011 can be used by setting scale_val_transfer_en = 1 ( bit5 of spiout_conf register 0x04) . using this feature , t he current scale parameter scale_param is sent via spi output to the motor driver . pre - settings ( made bef ore via cover datagrams ) become considered if the particular registers become overwritten with the new scaling value or with the new microstep resolution. the configuration of automatic scaling will be explained in chapter 12.6 . 12.5.3 configuration for the tmc389 3 - phase stepper driver if a tmc389 is connected to the spi output and a microstep resolution of 256 is set, a three phase stepper output for coil b can be generated. therefore, set three_phase_stepper_en = 1 ( bit4 of spiout_c onf register 0x04) . now, the currentb and currentb_spi values are shifted for 120 (instead of 90 for 2 - phase stepper motors). 12.5.4 chopsync ? configuration for tmc23x / tmc24x stepper driver s - connect the clock output signal stdby_clk of TMC4361 to the osc input of the tmc23x/24x stepper driver. (this input is used as pwm clock input.) now, the chopsync feature can be used for a fast and smooth drive. - set stdby_clk_pin_assignment = b 10 ( bit14:13 of general _conf register 0x00) to forward the internal chopsync ? cl ock to the stdby_clk output pin. - the clock frequency of the pwm is assigned by setting chopsync_div (0x1f) . the internal clock of TMC4361 is divided by this parameter to assign the pwm frequency f osc = f clk / chopsync_div with 96 chopsync_div 818. - if stdby_clk_pin_assignment = b 11 is set the internal clock is forwarded via stdby_clk and the c hopsync ? feature is not available .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 53 www.trinamic.com 12.5.5 motor driver status bits and stall detection when a tmc motor driver receives a current datagram (transmitted via the spi out put of the TMC4361) status data is sent back to the TMC4361 controller immediately. these responses from the driver are stored in the cover response register which consists of cover_drv_low (0x6e) and if necessar y cover_drv_high (0x6 f ) . additionally, motor driver status bits are forwarded to the status register. refer to chapter 19 for detailed information about status bits of tmc motor driver chips. e vents and i nterrupts b ased on m otor d river s tatus b its - the mstatus_selection ( bit23:16 of step_conf register 0x0a) can be set in a way that selected motor driver status bits release an motor event if a status bit becomes active. - for generating an interrupt the motor driver event events (3 0 ) can be configured as interrupt source. s t all d etection h andling - tmc motor driver chips always return the stall detection status to the TMC4361 motion controller in response to every received spi datagram. in most cases, one bit indicates that a motor stall occurred. - if ? stop_on_stall = 1 (bit26 o f reference_conf register 0x01) is set and ? | vactual | > vstall_limit (0x67) an active stall status is handled as a stop event with a hard stop. - the subsequently released stop_on_stall event immediately stops the currently valid velocity ramp. - for starting a new velocity ramp set drv_after_stall = 1 (bit27 of reference_conf register 0x01) . now, the stop_on_stall event becomes reset. - the drv_after _ stall switch has to be set back manually. a ttention as long as the current absolute velocity is below vstall_ limit , only the active_stall flag will be released and no hard stop will be executed. tmc26 xx , tmc21 xx /51 xx , and tmc389 motor driver status bits as response from current datagrams are received automatically. one stall detection status bit is returned to th e microcontroller in response to every received spi datagram. tmc24 x stall g uard c haracteristics the tmc24x forwards stallguard values (=ld2&ld1&ld0) instead of one stallguard status bit. the se bits represent an unsigned value between 0 and 7. t he lower th e value the higher is the mechanical load. by setting stall_load_limit (bit10:8 of spiout_conf register 0x04) properly, a stall is indicated when (ld2&ld1&ld0) stall_load_limit which result s in a hard stop if stop_on_stall = 1. set stall_flag_instead_of_uv_en = 1 (bit7 of spiout_conf register 0x04) to replace the undervoltage status bit in the status register w ith the stall status of tmc24x drivers. a standby datagram is sent to the tmc24x stepper driver if stdby_on_stall_for_24x = 1 (bit6 of spiout_conf register 0x04) and a stop_on_stall event occurs. this datagram sets current values to 0 which result s in a p ower down of the tmc24x motor driver.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 54 www.trinamic.com 12.6 connecting driver chips from other parties the TMC4361 provides also configuration data for driver chips of other companies via the cover registers . please note that the cover_data_length has to be set properly . fur thermore, it is possible to support automatic current data transfer. the following format settings can be chosen: output formats spi_output_format automatic current datagram transfer automatic cover register length (if cover_data_lengh =0) spi output off b 0000 - 1 signed current data b 0101 ? 1 unsigned scaling factor b 0100 - 1 dac scaling factor b 0110 - 1 dac absolute values b 0010 / b 0011 ? 1 dac adapted values b 0001 ? 1 c omments on the t able - spi_output_format = b 0000 switches off the spi output. - spi_output_format = b 0101 leads to a transfer of both signed current values one after the other in an 18 bit datagram. - with spi_output_format = b 0100, the 8 bit scaling factor is transmitted if it has been altered. th is scaling data could also be trans mitted for a dac by setting spi_output_format = b 0 1 10, assumed that the spi capabilities of the dac fit. - spi_output_format = b 0010 converts the current values for the spi capable dac into absolute values. the current phases of both coils are forwarded v ia the stpout (coila) and dirout (coilb) outputs. a phase bit polarity of 0 indicates a positive value. - spi_output_format = b 0011 converts the current values for the spi capable dac into absolute values. the current phases of both coils are forwarded via the stpout (coila) and dirout (coilb) outputs. a phase bit polarity of 0 indicates a negative value. - with spi_output_format = b 0001 the currents are mapped to an unsigned value. therefore, a value of 256 is added to the signed current values. thus, the current value 0 results in a 9 bit value of b10000000 whereas the minimum value of - 256 is exported as b000000000 and the maximum value of 255 as b111111111. - additionally fs_sdout can be set to 1 in case switching from microsteps to fullsteps and back is desired. dac v alue o ffset and l ength of d atagram - an offset can be added for the values of both coils by setting dac_offset (bit31:24 of register 0x7e) to compensate for a shifted base line . - usually, spi transfers require an address or a command in fron t of a transmitted value. the length of the prefixed command or address can be assigned by setting dac_cmd_length (bit11:7 of spiout_conf register 0x04) . - the bit stream which constitutes the command or address can be stored in the dac_addr register 0x1d w ith 16 bits for both coils separately. due to the transfer of only one value per datagram, two datagrams are sent in a row: first the coila command and value are sent and afterwards the coilb command and value. if the cover register length comprises more b its than the combination of command and value, zeros are added at the end. this is because the cover register length determines the length of the datagram for dac values. note that the command bits consist of the least significant bits of dac_addr if the c ommand length is less than 16 bit. c hanging spi o utput t ransfer c onditions sometimes, other spi output transfer conditions are required. therefore, further configuration is possible: - by setting sck_low_before_csn = 1 (bit4 of spiout_conf register 0x04) , s ckdrv_nsdo is tied low before nscsdrv_sdo. (per default setting, sckdrv_nsdo is tied high) - further on , tmc drivers sample the master data with the rising edge of the master clock. thus, TMC4361 shifts the output data at sdodrv_sclk with the falling edge o f sckdrv_nsdo. in case the data is sampled with the falling edge of the master clock at the drivers side, the data at sdodrv_sclk has to be shifted with the rising edge of sckdrv_nsdo. therefore, set new_out_bit_at_rise = 1 (bit5 of spiout_conf register 0 x04).
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 55 www.trinamic.com 12.7 current scaling & ramp status the current values of the microstep look - up table ms lut represent the maximum 9bit signed values which could be sent via the spiout output interface (values could be read out at register 0x7a - currenta at bit8:0 and cu rrentb at bit24:16). in most cases of the velocity ramp, it is not required to drive the motor with the full amplitude. various possibilities have been implemented to adapt the actual current values of the internal microstep look - up table ms lut to the cur rent ramp status whose signed values). scale parameters a re available for boost current , hold current, and drive current. these parameters could be assigned independently in the scale_values register 0x06 and will be used automatically for di fferent stat es of the velocity ramp if enabled : - boost scale value: boost_scale_val = scale_values (7:0) - drive scale value: drv1_scale_val = scale_values (15:8) - alternative drive scale value: drv2_scale_val = scale_values (23:16) - hold scale value: hold_scale_val = scale_values (31:24) the feasible scaling situations will be introduced after a brief explanation of the scaling calculation . if scaling is enabled for the current ramp state, the a ctual current values of the mslut will be multiplied with the mult_scale parameter , which is deduced from one of the four scale_param values : mult_scale = ( actual _ scale_val + 1) / 256 with actual = { hold , boost , drv1 , drv2 } . thus, a mult_scale parameter will be generated which ranges from 0 to 1: 0 < mult_scale 1 . combining this parameter with the maximum current values will result in the actual transferred current values which could be read out at register 0x7b: currenta_spi = currenta mult_scale = bit8:0 of 0x7b currentb_spi = currentb mult_scale = bi t24:16 of 0x7b as it could be seen, any value between 0 and the maximum current value available by the mslut entry could be sent using the scaling capability a ttention i f tmc drivers are used in stepdir output mode using spiout only for configuration ( sp i_output_format = b1011/b1100 and scale_val_transfer_en = 1), scaling values comprises only 5bit due to the fact that driver maximum scale value is 31 . thus, only the last five bits of the eight bit scaling registers are transferred in step/dir output mo de . furthermore, mult_scale is calculated at the driver devices using the following equation: mult_scale = (actual _scale_val + 1) / 32 . for scaling the current values during stand still two settings are available: s tandby s caling - set hold_current_scale_e n = 1. - the stdby_delay timer is started as soon as vactual reaches 0 . - in case the standby timer expires and vactual is still 0, standby mode is valid and currents are scaled down using hold_scale_val now . - in case stdby_delay is set to 0 standby mode is valid immediately after reaching vactual = 0. note : i f stdby_clk_pin_assignment (1) = 0 , the stdby_clk output pin forward s the standby signal with active polarity which is equal to the setting stdby_clk_pin_assignment (0). s caling for f reewheeling - for freewhe eling set freewheling_en = 1. - as soon as standby mode is reached , the freewheel_delay time r is started. it expires while standby mode remains active. - when freewheel_delay is elapsed, freewheeling mode becomes enabled and thus all current values are alter ed to 0. - in case freewheel_delay is set to 0, freewheeling mode becomes valid immediately after reaching standby mode.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 56 www.trinamic.com it is also possible to manipulate standard current values during the ramp: b oost s caling at r amp s tart - set boost_current_after_start_e n = 1 for scaling current values with boost_scale_val . - boost scaling at ramp start begins with the onset of a velocity ramp, assumed that vactual has been set to 0 before . - at the ramp start the boost_time (value represents a number of clock cycles ) becom es initialized . when this timer expires , boost scaling after start is finished. b oost s caling on a ccelera tion r amps - if ramp_state = b 01 and boost_current_on_acc_en = 1 are set , actual current values are scaled with boost_scale_val . - ramp_state = b 01 is a lways valid when the absolute velocity value increases. b oost s caling on d eceleration r amps - if ramp_state = b 10 and boost_current_on_dec_en = 1 are set , the actual current values are scaled with boost_scale_val . - ramp_state = b 10 is always valid when the absolute velocity value decreases. d rive s caling - if drive_current_scale_en is set to 1 , current values are scaled with drv1_scale_val , assumed that no other scaling mode is active at that moment . - in case sec_drive_current_scale_en = 1 is chosen additiona lly , drv1_scale_val is only used if the condition vactual vdrv_scale_limit is met. - if sec_drive_current_scale_en = 1, drive_current_scale_en = 1, and vactual > vdrv_scale_limit are valid , current values are scaled with drv2_scale_val , assumed that no other scaling mode is active. setup of scaling values for s tep /d ir operation with tmc21xx/51xx , tmx26xx, or tmc389 scaling values are transmitted directly to the driver in case step/dir output mode and scale_val_transfer_en = 1 is valid. please note that the maximum scale value is 31 due to the fact that scale val ues are stored as 5 bit numbers. thus, only the last 5 bits of the eight bit scaling registers are transferred in step/dir output mode . furthermore , mult_scale is calculated at the driver devices using the following equation: mult_scale = (actual _scale_va l + 1) / 32 controlling the transition process from one scale mode to another t he transition from one scale value to the next can be configured and has not to be abruptly. three parameter s are available for controlling the progression: up_scale_delay se t the period of clock cycles during which a current scale value is increased by one step towards the higher target scale value with up_scale_delay . hold_scale_delay set the period of clock cycles during which a current scale value is decreased by one step towards the lower target scale value hold_scale_val with hold _scale_delay . drv_scale_delay drv_scale_delay is the time period that is required to decrease the actual scale value towards a scale value which is smaller than the current one . setting any o f these parameters to 0 will result in an immediate transition to the next scale value for the introduced conditions. t he following two examples illustrate how scaling modes are to be used.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 57 www.trinamic.com e xample 1 standby scaling , freewheeling , boost scaling at start , boost scaling on deceleration ramps , and drive scaling i are enabled. current scale parameters ( scale_param ) are shown as well as their related scale timers in clock cycles . the timers are used to finish boost scaling after start and to start standby sca ling and freewheeling. the three depicted delay values are calculated as follow: t dn_scale = ( boost_scale_val - drv1_scale_val ) ? drv_scale_delay t up _scale = ( boost_scale_val - drv1_scale_val ) ? up_scale_delay t hold _scale = ( drv1_scale_val - hold_scale_val ) ? hold_scale_delay figure 12 . 5 scaling: e xample 1 e xample 2 boost scaling on acceleration ramps and both drive scaling modes are enabled . as long as vactual < vdrv_scale_limit , d rive scaling i is active. both drive scaling modes are used for the deceleration ramp due to boost_current_on_dec = 0 . when vactual reaches 0, the ramp_status switches to acceleration ramp and b oost scaling becomes enabled a second time. figure 12 . 6 scaling: example 2 v ( t ) t t s c a l e _ p a r a m b o o s t s c a l i n g d r v 1 s c a l i n g s t d b y s c a l i n g f r e e w h e e l i n g t s c a l e t i m e r [ c l k c y c l e s ] b o o s t _ s c a l e _ v a l d r v 1 _ s c a l e _ v a l h o l d _ s c a l e _ v a l s t d b y _ d e l a y f r e e w h e e l _ d e l a y b o o s t _ t i m e t d n _ s c a l e t u p _ s c a l e t d n _ s c a l e t h o l d _ s c a l e v ( t ) t t s c a l e _ p a r a m v d r v _ s c a l e _ l i m i t - v d r v _ s c a l e _ l i m i t b o o s t s c a l i n g d r v 1 s c a l i n g d r v 2 s c a l i n g b o o s t _ s c a l e _ v a l d r v 1 _ s c a l e _ v a l d r v 2 _ s c a l e _ v a l
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 58 www.trinamic.com 13 nfreeze: emergency - stop in case of dysfunctions at board level , s ome app lications require an additional strategy to end current operations without any delay . therefore, t he TMC4361 provides the low active safety pin nfreeze . p ins and r egisters : f reeze f unctionality pin names type remarks n freeze input external enable pin; low active register name register address remarks dfreeze 0x4e (23 ? 0) rw deceleration value in the case of an active freeze event ifreeze 0x4e (31 ? 24) rw current scaling value in the case of an active freeze event nfreeze is low active. an active nfreeze input transition from high to low level stops the current ramp immediately in a user configured way. at the moment when nfreeze switches to l ow, an event ( frozen ) is triggered at events (10). frozen remains active until the reset of the TMC4361. due to an input filter of three consecutive sample points it is necessary to tie nfreeze low for at least three clock cycles. 13.1 freeze function configur ation t wo parameters ( dfreeze and ifreeze ) are necessary for using the TMC4361 freeze function . they are integrated in the freeze register which can be written o nly once after an active reset, assumed that there has been no ramp started before . thus, the f reeze parameters should be set directly in the beginning of operation . note that the chosen values cannot be altered until the next active reset. these restrictions are necessary to protect the TMC4361 freeze configuration from incorrect spi data sent fro m the microcontroller in case of error . note t he polarity of the nfreeze input cannot be assigned. the freeze register can always be read out. during freeze state ramp register values can be read out. c onfiguring dfr eeze for an a utomatic r amp s top - set d freeze = 0 for a hard stop. - set dfreeze 0 for a linear deceleration ramp. due to the independence of dfreeze from internal register values like direct_acc_val_en or the given clock frequency clk_freq ( which can be a ltered by erroneous spi signals ) the deceleration value dfreeze is always giv en as velocity value change per clock cycle . therefore, the dfreeze value is calculated as follows : d_freeze[pps2] = dfreeze / 2 37 ? f clk 2 this leads to the same behavior of the motor as a direct_acc_val_en = 1 setting during normal operation . c onfiguring th e ifreeze c urrent s caling v alue ifreeze is a current scaling value which becomes valid in case nfreeze has been tied to low and the related event ( frozen ) has been released . in case ifreeze is set to 0 , the last scaling value before the emergency event is assigned permanently. the scale value ifreeze then manipulate s the current value in the same way as explained in chapter 12.6 .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 59 www.trinamic.com 14 controlled pwm o utput the TMC4361 allows for using pwm output values instead of step/dir outp uts. p ins and r egisters : pwm o utput pin names type remarks stpout_ pwma output pwm output for coil a dirout_ pwmb output pwm output for coil b register name register address remarks general_conf 0x00 rw bit 21: pwm_out_en current_conf 0x05 rw pwm_ampl( 31:16) if bit8 (pwm_scale_reg_chn)= 1 pwm_ampl 0x06 rw second assignment to scale_values ( 15 ? 0): pwm amplitude at vactual = 0 if bit8 (pwm_scale_reg_chn)= 1 pwm_vmax 0x17 rw second assignment to vdrv_scale_limit : velocity at which the pwm scale parame ter reaches 1 (max) pwm_freq 0x1f rw # of clock cycles which forms one pwm period 14.1 pwm output g eneration for generating a pwm output, set pwm_out_en = 1. now , the s tep /d ir output is disabled and pwm signals are forwarded via stpout_pwma and dirout_pwmb. t he pwm frequency is calculated as follows : f pwm = f clk / pwm_freq . the duty cycle for both coils is indicated by a high output level. for higher velocity a higher duty cycle is required. therefore, the TMC4361 alters a pwm scale parameter ( pwm_scale ) as a fu nction of the current velocity: - if vactual = 0, pwm_scale = ( pwm_ampl + 1) / 2 17 . - with increasin g velocity, the scale parameter raises linear to a maximum of pwm_scale = 0.5 at vactual = pwm_vmax . - the minimum duty cycle is calculated with duty_min = ( 0.5 C pwm_scale ). - t he maximum duty cycle is calculated with duty_max = (0.5 + pwm_scale). the current duty cycle for both coils is calculated using the microstep loop - up table mslut. in this case the mslut describes a voltage (co - )sine curve whose amplit udes become transferred to the pwm phases. the values are scaled related to minimum and maximum duty cycles. in the following illustration, the c alculation of minimum / maximum pwm duty cycles with pwm_ampl = 32767 is pointed out at the left side. resulting duty cycles for different positions in the sine voltage curve are depicted at the right side. c alculated delays of minimum / maximum duty cycles are also shown . figure 14 . 1 calculation of pwm duty cycles p w m _ s c a l e v a c t u a l p w m _ v m a x ( p w m _ a m p l + 1 ) 2 ^ 1 7 0 . 5 t d u t y _ c y c l e p w m _ v m a x p w m _ f r e q f c l k t d u t y _ m a x = ( 0 . 5 + p w m _ s c a l e ) ? p w m _ f r e q / f c l k t d u t y _ m i n = ( 0 . 5 C p w m _ s c a l e ) ? p w m _ f r e q / f c l k v a c t u a l t v o l t a g e ( v ) t t 0 . 5 ? p w m _ f r e q f c l k t i i i i i i i i i i i i
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 60 www.trinamic.com h int if a 2 nd assignment for scale_values should be avoided, pwm_scale_reg_chn have to be set to 1, then the pwm_ampl register is changed from register 0x06 scale_values(15:0) to register 0x05 current_conf(31:16). thus, switching between pwm and spi mode c ould be executed without any need to alter the scale settings.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 61 www.trinamic.com 15 support of the dcstep feature of tmc motor drivers dcstep is an automatic commutation mode for the stepper motor drivers. it allows the stepper to run with its nominal velocity taken from the ramp generator as long as it can cope with the motor load. in case the motor becomes overloaded, it slows down to a velocity, where the motor can still drive the load. this way, the stepper motor never stalls and can drive heavy loads as fast as possible. its higher torque available at lower velocity, plus dynamic torque from its flywheel mass allow compensating for mechanical torque peaks. in case the motor becomes completely blocked, the stall flag will be set. 15.1 essential pins and registers pin name pin ty pe remarks mp1 input dcstep input signal mp2 inout as output dcstep out put signal register name register address remarks general_conf 0x00 rw bit22 ? 21: dc_step_mode dc_vel 0x60 w velocity at which dcstep starts (fullstep); 24 bit dc_time 0x61 (7 : 0) w upper pwm on time limit for internal dcstep calculation dc_sg 0x61 (15 : 8) w maximum pwm on time for step loss detection (multiplied by 16!) dc_blktime 0x61 (31 : 16) w dcstep blank time after fullstep release dc_lsptm 0x62 w dcstep low speed timer; 32 bit 15.2 designing - in dcstep into an application in a classical application, the operation area is limited by the maximum torque required at maximum application velocity. a safety margin of up to 50% torque is required, in order to compensate for unforeseen load p eaks, torque loss due to resonance and aging of mechanical components. dcstep allows using up to the full available motor torque. even higher short time dynamic loads can be overcome using motor and application flywheel mass without the danger of a motor s tall. with dcstep the nominal application load can be extended to a higher torque only limited by the safety margin near the holding torque area (which is the highest torque the motor can provide). additionally, maximum application velocity can be increase d up to the actually reachable motor velocity. figure 15 . 1 : dcstep extended application operation area c l a s s i c o p e r a t i o n a r e a w i t h s a f e t y m a r g i n t o r q u e v e l o c i t y [ r p m ] d c s t e p o p e r a t i o n - n o s t e p l o s s c a n o c c u r a d d i t i o n a l f l y w h e e l m a s s t o r q u e r e s e r v e m i c r o s t e p o p e r a t i o n 0 m n o m 1 m m a x d c _ v e l v m a x m n o m : n o m i n a l t o r q u e r e q u i r e d b y a p p l i c a t i o n m m a x : m o t o r p u l l - o u t t o r q u e a t v = 0 a p p l i c a t i o n a r e a m a x . m o t o r t o r q u e s a f e t y m a r g i n d c s t e p e x t e n d e d s a f e t y m a r g i n : c l a s s i c a l a p p l i c a t i o n o p e r a t i o n a r e a i s l i m i t e d b y a c e r t a i n p e r c e n t a g e o f m o t o r p u l l - o u t t o r q u e m n o m 2
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 62 www.trinamic.com 15.3 enabling dcstep please refer to the corresponding manuals for the correct motor driver settings. desp ite particular motor settings which could be tunneled via spi through TMC4361, dcstep requires only a few settings. it directly feeds back motor motion to the ramp generator, so that it becomes seamlessly integrated into the motion ramp, even if the motor becomes overloaded with respect to the target velocity. dcstep operates the motor in fullstep mode at the ramp generator target velocity vactual or at reduced velocity if the motor becomes overloaded. by setting dc_step_mode (1) = 1, dc step will be enabl ed for tmc26x drivers ( dc_step_mode (0) = 1) or for tmc21xx drivers ( dc_step_mode (0) = 0). if one of both already chosen for spi_output_format , dc_step_mode could be set to 01 which will automatically select the correct dcstep module. dcstep requires setting the minimum operation velocity dc_vel . dc_vel shall be set to the lowest operating velocity where dcstep gives a reliable detection of motor operation. if an overload appears, an internal dcstep signal will be generated which paused the internal st ep generation. after dc_lsptm clock cycles expires without lifting the internal dcstep signal, a step will be enforced to remain a minimum step frequency of f clk / dc_lsptm . figure 15 . 2 : velocity profile with impact by overload situation 15.3.1 dcstep with tmc21xx dcstep operation with tmc21xx is similar to an handshake procedure. if vactual dc_vel , mp2 output will be set to 1 to indicate that dcstep is possible. tmc21xx will wait for the next fullstep position to switch to dcstep operation. the dcstep signal will be provided by the tmc21xx itself. this signal will be supplied by the mp1 input pin. if mp1 is low, an overload is occurred. this will pause the internal step generator. i f mp1 will stay low until dc_lsptm clock cycles have been expired, the TMC4361 will generate an step with a step length of 4096 clock cycles to enforce tmc21xx generating a step. 15.3.2 dcstep with tmc26x connected to tmc26x drivers, TMC4361 have to generate the dcstep signal internally. therefore, the dcstep_stall input has to be connected to sg_tst output pin of the tmc26x driver. furthermore, the tst_mode pin of tmc 26x have to be tied to vdd and following tmc26x settings have to be made: chm = 1, hstrt = 0, tst = 1 and sgt0 = sgt1 = 1. the internal dcstep signal will approve further step generation if the input step signals of the dcstep_stall input pin will be smaller than the dc_time step length in clock cycles which should be slightly higher than chopper blank time tbl. while dcstep is able to decelerate the motor upon overload, it cannot avoid a stall in every operation situation. once the motor is blocke d, or it becomes decelerated below a motor dependent minimum velocity where the motor operation cannot safely be detected any more, the motor may stall and loose steps. in order to safely detect a step loss and avoid restarting of the motor, the stop on st all can be enabled (see stop_on_stall ). in the case of dcstep operation with tmc26x the stall bit from the driver v ( t ) t d c s t e p a c t i v e d c _ v e l 0 v b r e a k v m a x a m a x d m a x d f i n a l a s t a r t n o m i n a l r a m p p r o f i l e r a m p p r o f i l e w i t h t o r q u e o v e r l o a d a n d s a m e t a r g e t p o s i t i o n o v e r l o a d
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 63 www.trinamic.com status will be substituted by the dcstep stall detection bit. therefore, the first step of dcstep_stall after an step release will be checked against the dc_sg value which is the maximum pwm on time. if the signal step length is smaller than dc_sg a stall has occurred. dc_blktime specifies the number of clock cycles after a fullstep release when nothing will be compared due to possible fragmente d steps which will be sent over mp1 . the first step after release which will checked is the first step after the blank time. the switch to fullstep drive will be done automatically as explained in chapter 12.5. a ttention all settings as regards dcstep sho uld be made before beginning dcstep operation! h int it is possible to transfer automatically cover datagrams to the tmc26x (see 12.3 ). thereby, it is possible to switch rapidly the chopper settings of the tmc26x shortly before reaching the dcstep velocity. it is recommended to use this feature as dcstep requires const toff chopper settings whereas driving with steps and a spreadcycle chopper provides better driving characteristics. therefore, s et spi_switch_vel a little bit sm aller than dc_vel and turn on automatic_cover. after transferring all required cover datagrams, fill in cover_low the chopper settings for spreadcycle below the dc_vel . in cover_high the consttoff settings for the chopper during dcstep (fullsteps) should b e filled in.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 64 www.trinamic.com 16 decoder unit & closed loop the TMC4361 is equipped with an encoder input interface for incremental ab n encoders or absolute encoders like ssi, spi , or biss encoders. m otor feedback can be analyzed and even closed loop behavior can be reache d by setting the registers appropriately. p ins and r egisters : d ecoder u nit pin names type remarks a_sclk input or output a signal of abn encoder or serial clock output for ssi, spi or biss encoder s aneg_nsclk input or output negated a signal of abn enco der or negated serial clock output for ssi / biss encoder or low active chip select signal for spi encoder s b_sdi input b signal of abn encoder or serial data input of ssi, spi or biss encoder s bneg_nsdi input or output negated b signal of abn encoder or negated serial data input of ssi / biss encoder s or serial data output of spi encoder n input n signal of abn encoder nneg input negated n signal of abn encoder register name register address remarks general_conf 0x00 rw bit11 ? 10 serial_enc_in_mode bit12 diff_enc_in_disable input _filt_conf 0x03 rw input filter configuration ( sr_enc_in, filt_l_enc_in ) enc_in_conf 0x07 rw encoder configuration register enc_in_data 0x08 rw serial encoder input data structure step_conf 0x0a rw motor configurations enc_pos 0x50 rw current absolute encoder position in microsteps enc_latch 0x51 r latched absolute encoder position enc_pos_dev 0x52 r deviation between xactual and enc_pos enc_const 0 x5 4 r internally calculated encoder constant encoder register set 0x 5 158 0x6263 w encoder configuration parameter encoder velocity 0x65 0x66 r current encoder velocity (unsigned) current filtered encoder velocity (signed) addr_to_enc data_to_enc 0x68 0x69 w serial encoder request data addr_from_enc data_from_enc 0x6a 0 x6b r serial encoder request data response encoder compensation 0x7d w encoder compensation register set register name register address remarks closed loop settings 0x1c 0x59 rw c losed loop / pid configuration parameter 0x5a5f 0x6061 w 0x5a..5d r pid control parameter closed loop scaling settings 0x181a rw c losed loop configuration parameter for current scaling current_conf 0x05 rw bit7 closed_loop_scale_en scale_values 0x06 rw current scaling values and limits for closed loop operation
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 65 www.trinamic.com 16.1 g eneral encoder interface the encoder interface consists of six pins (a_sclk, aneg_nsclk, b_sdi, bneg_nsdi, n, nneg) . for configuration set serial_enc_in_mode . n and nneg are only required for incremental encoder s. all encoder input signals become filtered using the digital filter introduced in chapter 6 . thus, sr_enc_in and filt_l_enc_in have to be set properly. c hoosing the s erial e ncoder _in m ode serial_enc_in_mode = b 00 : abn incremental encoder setting. a ll six interface pins are inputs . s ignals are interpreted as abn sig nals of an incremental encoder. serial_enc_in_mode = b 01 : absolute ssi encoder setting. a_sclk and aneg_nsclk are outputs w hich forward the master clock signal s to the motor encoder interface. o nly b_ sdi and bneg_ nsdi are required inputs to receive data from the encoder . serial_enc_in_mode = b 10 : a bsolute biss encoder setting . a_sclk and aneg_nsclk are outputs which provide the master clock signal to the motor encoder interface. o nly b_ sdi and bneg_ nsdi are required as inputs to receive data from the encoder. serial_enc_in_mode = b 11 : a bsolute spi encoder setting . a_ sclk is the serial clock output, aneg_ nsclk is the low active chip select output, b_ sdi function s as serial data input from the spi encoder , and bneg_nsdi is the serial data output.. diff_enc_in_disable is set automatically to 1 . h ow to e nable or d isable d ifferential e nc oder s ignals diff_enc_in_disable = 0 differential encoder interface inputs are enabled. differential inputs are treated as digital differential inputs. for advertizing a val id level the levels have to be inversed. diff_enc_in_disable =1 differential encoder interface inputs are disabled. for spi encoders this is done automatically. s ignals are handled as single signals and e very negat ed pin becomes ignored . 16.2 incremental abn e ncoder the i ncremental abn encoder increment s or decrement s the internal enc_pos counter . this is based on a and b signal level transitions. abn encoder configuration 1. choose the number of microsteps per ab transit ion: - s et the fullstep resolution of the motor with fs_per_rev and the microstep resolution mstep_per_fs for the drive r in the step_conf register 0x0a . - then , set the encoder resolution with enc_in_res . 2. choose the direction of the encoder with invert_enc _in . set 1 for inverting if desired. 3. verify the encoder constant. enc_const is calculated automatically , if the settings for fs_per_rev , mstep_per_fs , and enc_in_res fit properly. enc_const gives the numbe r of microsteps which are added or subtracted fro m enc_pos (dependent on the direction) with every ab transition. it is calculated with enc_const = mstep_per_fs ? fs_per_rev / enc_in_res enc_const can be read out. i t consists of 15 digits and 16 decimal places. if 16 bit are not sufficient for a binary representation of the decimal places , TMC4361 tries to match them to a multiply of 10000 within these 16 decimal places . this way, a perfect match can be achieved in case decimal representation is preferred to a binary one . if also the decimal representati on does not fit completely, the type of the decimal places of enc_const can be chosen by hand with enc_in_conf (0). set enc_in_conf (0) to 0 for the binary re presentation or set it to 1 for the decimal one. but beware, this way enc_pos could be slightly diff erent to the real position. h int enc_const could also be set manually. it is recommended to use the equation above for the manual calculation. therefore, bit31 of the register 0x54 have to be set to 1. this way, writing to 0x54 do not represent enc_in_r es , instead it is the direct assignment of enc_const in this register 0x54.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 66 www.trinamic.com 16.2.1 n signal resp. z channel the n signal (or z channel) is either used to clear the position counter or to take a snapshot. the following configuration parameters are provided: pol _n set the active polarity with this parameter . n_chan_sensitivity set n_chan_sensivity for special requests: 00 n event is active if the voltage level at n fits pol_n 01 n event is triggered at the positive edge when n becomes active. 10 n event is tri ggered at the negative edge when n becomes active. 11 n event is triggered at both edges when n becomes active and/or inactive. pol_a_for_n , pol_ b _for_n some encoders require a validation of the n signal at a certain configuration of a and b polarit ies . t his can be controlled by pol_a_for_n and pol_b_for_n switches in the enc_in_conf register. when, e.g., pol_a_for_n and pol_b_for_n are set , an active n event is only accepted if the polarity of the a channel and the b channel is high. ignore_ab set ignore_ ab = 1 to disable the validation of the n signal via a and b channel polarity. then , these channel polarities have no influence on the n signal event. latch_enc_on_n set la tch_enc_on_n = 1 to monitor the encoder position enc_pos on an active n event. still , additional switches are required to monitor the encoder position. r efer to clr_latch_cont_on_n and clr_latch_once_on_n. clear_on_n to clear the encoder position enc_pos on the next n event set clear_on_n = 1. again , a dditional switches are required to cl ear enc_pos . r efer to clr_latch_cont_on_n and clr_latch_once_on_n. clr_latch_cont_on_n set clr_latch_cont_on_n = 1 to clear or monitor continuously on an active n event. clr_latch_once_on_n set clr_latch_ once _on_n = 1 to clear or monitor on an active n ev ent only once. after latching and/or clearing the encod er position clr_latch_once_on_n is disabled automatically. this is necessary if only the next of periodic n events (e.g. once for every revolution ) should be considered . latch_x_on_n set latch_x_on_n = 1 to monitor xactual on x_latch . t he tasks of encoder latching are adopted for x_latch . please note that latch_enc_on_n has to be set just as clr_latch_cont_on_n or clr_latch_once_on _n . h int for clearing the encoder position enc_pos with the next activ e n event set clear_on_n = 1 and clr_latch_ once _on_n = 1 or clr_latch_cont_on_n = 1. figure 16 . 1 outline of abn signals of an incremental encoder a b t p o s i t i o n - 4 - 3 - 2 - 1 0 5 6 4 3 2 1 7 n
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 67 www.trinamic.com 16.3 absolute e ncoder in this chapter, common settings for ssi , spi, and biss encoders are explained. specific i nformation about respective serial encoders is given in subsections. s erial encoders provide absolute encoder data instead of step transition , wh ose information is delivered from incremental e ncoders. due t o the serial data input the TMC4361 provides an external clock for the encoder. the TMC4361 provides different possibilities for the serial data stream . single turn data or multi turn data can be used. in case single turn data is transmitted the TMC4361 i s able to calculate the number of revolutions permanently. c hoosing e ncoder d ata and d ata t ype for t ransmission multi_turn_ in_ en in case multi_turn_en = 1 the serial encoder transmits the actual motor angle as well as data about the number of revolutions. if set to 0, the serial encoder transmits only the actual motor angle (single turn). multi_turn_in_signed in case it is desired to interpret the data about the number of revolutions as a signed value, set multi_turn_in_signed = 1. otherwise it is assigned as unsigned value. calc_multi_turn_behav for calculating the number of rev olutions out of single turn data set calc_multi_turn_behav = 1 and multi_turn_in_en = 0. in case two sequenced values differ in more than half a revolution, switch calc_multi_turn_b ehav off because the calculation will provide false data. the encoder constant enc_const is calculated the same way as for incremental abn encoders. but i n contrast to abn encoder s it always represent s a binary value . the value is multiplied with the tran sferred angle value for calculating the microstep position , which is stored in enc_pos afterwards . enc_const is generated automatically, if the settings for fs_per_rev , mstep_per_fs , and enc_in_res fit properly. it is calculated as follows: enc_const = mst ep_per_fs ? fs_per_rev / enc_in_res h int enc_const could be read out . i t consists of 15 digits and 16 decimal places in case a serial encoder is selected . s ettings r elated to d ata t ransmission single_turn_res set the number of bits for single turn data he re. single_turn_res defines the most significant bit ( msb ) . the number of angle data bits within one revolution is single_turn_res + 1. multi_turn_res set the number of bits for multi turn data here. multi _turn_res defines the most significant bit ( msb ) . t he number of data bits for revolution count is multi _turn_res + 1. information about the number of rotations is always expected to be sent before actual motor angle data! status_bit_cnt set the number of status bits which are transmitted from the encoder h ere. status bits consist of three bits at maximum. left_aligned_data this parameter is used to choose a sequential arrangement for status and serial input data. set left_aligned_data =0 for receiving the flags first and then the input data. set left_aligne d_data =1 for serial input data first and flags afterwards. serial_enc_variation_limit if erroneous data transmission from the encoder is expected, set serial_enc_variation_limit = 1. now, the difference s of sequenced encoder values become calculated. if a difference between two values exceeds one eighth of enc_in_res , the last encoder data is skipped. the multi_cycle_fail_f status flag becomes set and the ser_enc_data_fail event becomes triggered. as a result, calc_multi_turn_behav can be used with no dou bt due to the fact that the values never differ in more than half a revolution.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 68 www.trinamic.com a ttention generating a clock which requires more than the given serial bit range if more than three status bits or additional fill bits are sent , clock errors can occur becau se the number of transferred clock bits is calculated by #serial_clock_cycles = ( single_turn_res + 1 ) + ( multi_turn_res + 1 ) + status_bit_cnt . in order to prevent clock failures multi_turn_res can be set to a higher value than required, even if no multi t urn data is provided . note that t his setting may result in erroneous multi turn data . this can be corrected by setting multi_turn_ in_ en = 0 for skip ping multi turn data automatically . further, calc_multi_turn_behav can be set to 1 for compensating unavail able multi turn data. 16.3.1 ssi e ncoder serial clock after indicating data transfer by switching the clock output to low level, the transfer starts with the next rising edge of the serial clock output . the periods for low level and for high level have to be set separately using ser_clk_in_low and ser_clk_in_high which are given in internal clock cycles. s tart /e nd d elay t ime sample points of serial data are set at the falling edges of the serial clock. some encoders need more clock cycles than the low clock phas e to prepare data for transfer. further, due to long wires data transfer can take more time. considering these points, the delay time for compensation ssi_in_clk_delay can be specified in clock cycles and the parameter delays the sampling start. due to the delay, more clock cycles of the serial clock can be required which is automatically taken into account. per default, ssi_in_clk_delay is set to 0 and therefore ser_clk_in_high is valid instead. d elay t ime between s equenced d ata r equests after a data requ est the next one is sent past s er _ptime clock cycles. choose the value of this parameter higher than 21 s . figure 16 . 2 ssi signals with ssi_in_clk_delay = ser_clk_in_high when ssi_in_clk_delay=0 figure 16 . 3 ssi signals with ssi_in_clk_delay for compensating processing time and long wires r epeated d ata t ransfer (m ulti c ycle r equest ) if a repeated data transfer is requested, set ssi_multi_cycle_data = 1 . furth er, adjust ssi_in_wtime . this parameter configures the waiting time between two equal data requests (t he same value becomes transferred more than once ) . set the ssi_in_wtime smaller than 19 s. l s b m s b s a m p l e p o i n t s s e r i a l d a t a i n s e r i a l c l o c k o u t s e r _ c l k _ i n _ h i g h s e r _ c l k _ i n _ l o w m s b l s b - - - s a m p l e p o i n t s s e r i a l d a t a i n s e r i a l c l o c k o u t s s i _ i n _ c l k _ d e l a y
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 69 www.trinamic.com if two data values that normally must be equal ( due to the mul ti cycle data request ) are not equal, the multi_cycle_fail_f flag and the ser_enc_data_fail event are generated , assumed that serial_enc_variation_limit is 0. g ray e ncoded d ata s treams serial data streams can be gray encoded. set ssi_gray_code_en to 1 in o rder to decode them properly. 16.3.2 spi e ncoder the number of bits per transfer is calculated automatically . therefore, set single_turn_res , multi_turn_res , and status_bit_cnt properly . c ommunication p rocess typically , the answer of spi data transfer requests is sent with the next transmission. when the TMC4361 receives the answer from the encoder, it calculates enc_pos immediately . the encoder slave does not send any data without receiving a request first. therefore, the TMC4361 always sends the addr_to_enc va lue to request encoder data from the spi encoder slave device. t he lsb of the serial data output is addr _to_ enc (0). the clock is generated by the values given from ser_clk_in_high and ser_clk_in_low . the msb results from the number of bits that are requir ed for the whole transmission: msb spi_enc = ( single_turn_res + 1 ) + ( multi_turn_res + 1 ) + status_bit_cnt - 1. with the s er_p time register a time period after the last request can be set. during this period no further data transfer becomes initiated . s t oring e ncoder v alues r eceived encoder data is stored in addr_from_enc . thus, encoder values can be verified and compared to microcontroller data later on . spi data transfer within the current transmission for applications providing a response to spi data transfer requests within the current transmission , suggestions explained in generating a clock which requires more than the given serial bit range (see chapter 0 ) are valid . therefore, multi_turn_res has to be expanded for reac hing the required data length. further, the first bits of b_sdi must be zero if the multi turn data of the data transfer should also be evaluated. this way, proper evaluation of incoming data is guaranteed. f urther s ettings related to e ncoder t ype s per de fault, spi encoder data transfer is managed just as the communication between microcontroller and TMC4361. for supporting all spi encoder types, the TMC4361 provides further settings : spi_low_before_cs set this parameter to 1 if the spi clock has to be l ow before chip select switches to low level. spi_data_on_cs set this parameter to 1 for sending the msb of the data output with the transition of the chip select signal to active level. thus, bneg_nsdi provides output data immediately at aneg_nsclk trans ition. if set to 0, the data is sent after the first transition of the clock signal. in both cases data from b_sdi becomes sampled at the next clock transition. to achieve a correct synchronization, it is possible to choose ssi_in_clk_delay > 0 . thus, a delay time for ser_clk_in_high and ser_clk_in_low can be defined . this delay setting can be considered in case the clock scheme provided by ser_clk_in_high and ser_clk_in_low does not fit perfectly to the delay between the first and the last transition of signals of the chip select (aneg_nsclk) and the clock output (a_sclk) . ssi_in_clk_delay is shown in figure 16 . 4 as red lined distances. the following diagrams are examples for different spi_data_on_cs and spi_low_before _cs se ttings.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 70 www.trinamic.com spi_low_before_cs 0 1 spi_data_on_cs 0 1 figure 16 . 4 supported spi encoder data transfer modes spi e ncoder c onfiguration via TMC4361 the spi encoder can be configured by the TMC4361. thus , a connection between microcontroller and encoder is not necessary any more . a c onfiguration request is sent using the settings of the serial_addr_bits and serial_data_bits which define the transferring bit numbers . due to repeated encoder data reques ts a call for configuration has to be done in the meantime . therefore, data_to_enc can be used for configuration while the continuous requests for encoder data are interrupted during configuration process. p roceed as follows 1. write access to data_to_enc to notify a configuration request . 2. write the requested address to addr_to_enc . 3. write the requested data to data_to_enc . 4. now, t hree datagrams are sent to the spi encoder: - the address data from addr_to_enc (data from encoder is not stored) . - the register data fr om data_to_enc ( the received data from the encoder is stored in addr_from_enc ) . - a no - operation datagram ( nop ) to get the answer from the encoder ( which becomes stored in data_from_enc ) . 5. now, returned and stored data from the encoder can be read out and che cked by the microcontroller. read out addr_from_enc first. 6. write the required address for the continuous encoder value requests to addr_to_enc. 7. read out data_from_enc to finish configuration process. afterwards, repeated data request s become initiated imme diately. h int no further encoder value request becomes sent before data_from_enc has been read out ! sample points ( b _ sdi ) serial data out ( bneg _ nsdi ) serial clock out ( a _ sclk ) chip select ( aneg _ nsclk ) msb lsb sample points ( b _ sdi ) serial data out ( bneg _ nsdi ) serial clock out ( a _ sclk ) chip select ( aneg _ nsclk ) msb lsb sample points ( b _ sdi ) serial data out ( bneg _ nsdi ) serial clock out ( a _ sclk ) chip select ( aneg _ nsclk ) msb lsb sample points ( b _ sdi ) serial data out ( bneg _ nsdi ) serial clock out ( a _ sclk ) chip select ( aneg _ nsclk ) msb lsb
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 71 www.trinamic.com 16.4 regulation possibilities with encoder f eedback the encoder feedback can be used for controlling the motion controller outputs in a way that the internal actual position matches or rather follows the real position enc_pos . generally, two possibilities for position control are provided: pid control and closed loop operation. closed loop operation is a very good choice in case the encoder is mounted directly on the back of the motor and position data is evaluated precisely, whereas pid control is well suited where the encoder is located at the drive side and no fixed connection between motor and drive side is given, e.g. belt drives. the following regulatio n_modus settings are provided: regulation_modus = b10 use this setting for a pid control unit (with pulse generator base = 0). regulation_modus = b11 use this setting for a pid control unit (with pulse generator base = vactual .) regulation_modus = b01 u se this setting for closed loop operation. if pid regulation is no t selected ( regulation_modus (1) = 0) , the internal velocity which delivers the input for the pulse generato r is equal to the ramp velocity ( vel_act_pid = vactual ) . t arget r eached during r eg ulated b ehavior if one of the regulation modes is selected, target_reached event and flag will only be released if xactual = xtarget and if the encoder position enc_pos and the internal xactual are only differ at the most for tr_tolerance microsteps . reach ing xactual = xtarget and the difference exceeds the limit, the target_reached event or flag will occur not before the difference is decreased below the limit which could be done by the regulation itself (recommended!) or by setting enc_pos manually (not r ecommended!). 16.4.1 pid based c ontrol of xactual b ased on a position difference error pid_e = xactual C enc_pos t he pid (proportional integral d ifferential) controller calculates a signed velocity value ( v pid ) which is used for minimizing the position error. dur ing this process , the tmc4 361 moves with v pid until | pid_e | C pid_tolerance 0 is reached and the position error is removed . v pid is calculated by: ? ??? = ??? _ ? 256 ? ??? _ ? ? [ 1 ? ] + ??? _ ? 256 ? ??? _ ? ? ?? ? 0 + ??? _ ? ? ??? _ ? ? ? ?? ? ??? = ??? _ ? 256 ? ??? _ ? ? [ 1 ? ] + ??? _ ? 256 ? ??? _ ???? + ??? _ ? ? ??? _ ? ? ? ?? ? ??? = ??? _ ? 256 ? ??? _ ? ? [ 1 ? ] + ??? _ ? 256 ? ??? _ ? ? ? ??? 128 + ??? _ ? ? ??? _ ? ? ? ?? w ith pid_p = proportional term pid_i = integral term pid_d = derivate term c ontrol p arameters and c lipping v alues pid_dv_clip to avoid large velocity variations, the v pid value can be limited with pid_dv_clip . this clipping parameter limits v pid as well as pid_vel (current pid velocity output). pid_i_clip the error sum pid_isum is generated by the integral term. for limiting pid_isum set pid_i_clip . note that the maximum value of pid_i_clip should meet the condition pid_i_clip pid_dv_clip / pid_i . if the error sum pid_isum is not clipped, it is increased with each time step by pid_i ? pid_e . this continues as long as the motor does not follow. pid_e use this register for reading out the actual position deviation between xactu al and enc_pos . pid_d_clkdiv time scaling for deviation (with respect to error correction periods ) is controlled by the pid_d_clkdiv register. note that during error correction the fixed clock frequency f pid_integral [hz] = f clk [hz] / 128 is valid.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 72 www.trinamic.com vel_act _pid the internal velocity vel_act_pid alters the current ramp velocity vactual . two settings are provided: if regulation_modus = b 11 , vactual is assigned as pulse generator base value and vel_act_pid is calculated by vel_act_pid = vactual + v pid . if regulation_modus = b 10 , zero is assigned as pulse generator base value . i n this case vel_act_pid = v pid is valid. pid_tolerance the TMC4361 provides the programmable hysteresis pid_tolerance for target position stabilization. oscillations due to error co rrection can be avoided if xactual is close to the real mechanical position. the pid controller of the TMC4361 is programmable up to approximate 100khz update rate at f clk = 16 mhz . this high speed update rate qualifies it for motion stabilization . note t hat detailed knowledge of a particular application (including dynamics of mechanics) is necessary for pid controller parameterization which is done in a direct way ! 16.4.2 closed loop b ehavior t he closed loop unit of the TMC4361 modifies output current s resp. s te p /d ir output s directly . for closed loop , set regulation_modus = b 01. after starting this mode of operation , the closed loop calibration becomes executed and the cl_offset value becomes set . with closed loop, c urrent values are not controlled using the in ternal step generator . the currents values at the spi output resp. the step/dir outputs are verified using the closed loop offset value cl_offset which correlates to the evaluated difference between xactual and enc_pos . nevertheless, the internal ramp gene rator still generate s steps for xactual . b asic p arameters for c alibration and p osition d eviation c ompensation cl_offset the cl_offset register contains the offset value which is necessary for closed loop operation and offers read - write access. use the wri te access in case it is desired to define a fixed offset value which has been tested first. cl_calibration_en set cl_calibration_en = 1 to update/reset cl_offset . for evaluation of a proper value , be sure to meet the following conditions: - m aximum curren t without scaling is used . - vactual is set to 0 . - xactual refers to a motor fullstep position . enc_pos_dev the deviation parameter enc_pos_dev contains the deviation between xactual and enc_pos . cl_beta cl_beta is t he maximum commutation angle which c an be used to compensate an evaluated deviation enc_pos_dev . if the cl_beta value becomes reached due to a large difference in microsteps, the cl_max event becomes triggered. cl_tolerance set this parameter to choose a tolerance range for position deviati on. in case the cl_tolerance value is not exceeded and | enc_pos_dev | < cl_tolerance the cl_fit_f lag becomes set . if there has been a mismatch between xactual and enc_pos before, the cl_fit event becomes triggered in order to indicate that everything fits n ow. note : cl_tolerance is part of pid_tolerance . a pid_tolerance value is automatically chosen if the eight lower cl_tolerance bits are set . the pid_tolerance parameter contains 20 bits. the upper 12 bits can be used for further pid_tolerance adjustment for the pi controller which sets the upper limit for the error correction velocity during closed loop operation. cl_delta_p cl_delta_p is a proportional controller for compensating a detected position deviation. as soon as | enc_pos_dev | > cl_tolerance the closed loop unit of the TMC4361 mu ltiplies enc_pos_dev with cl_delta_p and adds the result ing value to the current enc_pos . thus, a current commutation angle for higher stiffness for position maintenance clipped at cl_beta becomes calculated.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 73 www.trinamic.com cl_delta_p consists of 24 bits . the last 16 bits represent decimal places. figure 16 . 5 depicts how register values affect the final output angle at step/dir and/or spi. t he final proportional term is calculated by ? ??? = ?? _ ????? _ ? 65536 note: t he higher the p pid term the faster the reaction on position deviations ! a high p pid term can lead to oscillations which should be avoided. as long as enc_pos_dev is in the range of xactual cl_tolerance , the pr oportional term is automatically set to 1 . if | enc_pos_dev | > cl_ beta , the cl_max event triggers assumed that | enc_pos_dev | < cl_ beta has been valid before . figure 16 . 5 calcula tion of the output angle by setting cl_delta_p properly. e rror c ompensation in c ase of l arger d eviations in case a deviation enc_pos_dev between x _actual and enc_pos exceed s the certain limit enc_pos_dev_tol , xactual becomes set to the enc_pos value , assum ed that cl_clr_xact is set to 1 . exceeding enc_pos_dev_tol always set s a status flag enc_fail_f and triggers the enc_fail event. v elocity r egulation p arameters to limit catch - up velocities in case a disturbance of regular motor motion has to be compensated the following parameters can be adjusted. cl_vlimit_en set cl_vlimit_en = 1 for limiting the maximum step velocity during closed loop operation . by setting cl_vmax_calc_p and /or cl_vmax_calc_i accordingly, a pi controller becomes used for velocity regul ation of the current ramp . the pi controller calculates the maximum step velocity which is subsequently generated by the closed loop unit. cl_vmax_calc_p p parameter of the pi regulator which controls the maximum velocity . cl_vmax_calc_i i parameter of th e pi regulator which controls the maximum velocity . pid_dv_clip to a void large velocity variations and to limit the maximum velocity deviation above the maximum velocity vmax , pid_dv_cli p can be set. pid_dv_clip is used with closed loop and for pi d contr olled operation. pid _i_clip together with pid_dv_clip t his parameter is used for limiting the velocity for error compensation . the error sum pi d _isum is generated by the e n c _ p o s _ d e v [ s t e p s ] n e w o u t p u t a n g l e e n c _ p o s + 4 5 ( + 1 2 8 s t e p s ) e n c _ p o s + 9 0 ( + 2 5 6 s t e p s ) e n c _ p o s - 9 0 ( - 2 5 6 s t e p s ) e n c _ p o s - 4 5 ( - 1 2 8 s t e p s ) 1 2 8 ( 4 5 ) 2 5 6 ( 9 0 ) 3 8 4 ( 1 3 5 ) - 1 2 8 ( - 4 5 ) - 2 5 6 ( - 9 0 ) - 3 8 4 ( - 1 3 5 ) p p i d = 1 p p i d = 1 p p i d = 2 p p i d = 2 p p i d = 4 p p i d = 4 0 C c l _ t o l e r a n c e c l _ t o l e r a n c e c l _ b e t a C c l _ b e t a
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 74 www.trinamic.com integral term. for limiting , set pid_i_clip . t he maximum value of pid_i_clip should me et the condition pid_i_clip pid_dv_clip / pid_i . if the error sum pid_isum is not clipped, it is increased with each time step by pid_i ? pid_e . this continues as long as the motor does not follow. the parameter pid_dv_clip is used with closed loop and for pi d controlled operation . in case position deviation at the end of an internal ramp calculation is still left, the spi and/or step/dir output ramp for correction is a linear deceleration ramp, independently from the preset ramp type. this final ramp for error compensation is a f unction of enc_pos_dev and pi control parameters ( cl_vmax_calc_p , cl_vmax_calc_i , pid_i_clip , and pid_dv_clip ) . due to the usage of a pi controller for the maximum velocity, the velocity offset depends on enc_pos_dev . it is recommended to set a limit for t he error correction velocity using pid_dv_clip and pid_i_clip . h int n ote that a higher velocity than vmax resp. - vmax is possible if the following conditions are met: - the pi controller is enabled and pid_dv_clip > 0. - cl_vmax_calc_p and cl_vmax_calc_i are higher than 0 . - enc_pos_dev > cl_tolerance resp. enc_pos_dev < cl_tolerance . c losed l oop v elocity mode for some application it is only required to hold the maximum velocity no matter of the position deviation. this could be reached by setting cl_velocity_ mode_en = 1. if this mode is switched on, the current position xactual will be reset to ( cl_beta C 1) as soon as | xactual C enc_pos | cl_beta . by activating the velocity regulation parameters ( cl_vlimit_en = 1) and setting pid_dv_clip slightly higher than 0, the position deviation will recover as soon as the cause of the position mismatch will disappear. setting pid_dv_clip > 0 will lead to slightly higher velocity than vmax during recovering to vactual = vmax which could be unwanted. but setting pid_dv_cl ip = 0 will not overhaul the position deviation and a small value of pid_dv_clip will almost not be recognized. h ow to b enefit from the s caling u nit the TMC4361 provides a scaling unit which can be used during closed loop operation . therefore, set closed _loop_scale_en to 1. h ow the scaling unit works 1. to decrease current consumption if xactual and enc_pos match , set cl_imin to an appropriate value which is the valid scaling value as long as | enc_pos_dev | c l_start_up . 2. in case the threshold value c l_star t_up is exceeded , the current scaling value becomes increased linearly until | enc_pos_dev | = cl_beta . 3. if | cl_beta | is overshot also, cl_imax is the valid current scaling value. h int note that any other scaling becomes disabled if closed loop scaling is e nabled!
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 75 www.trinamic.com figure 16 . 6 current scaling in with closed loop in case cl_start_down is set to 0, cl_beta is the starting point for downscaling. in contrast to the up scaling process th e start of downscaling can differ from cl_beta . b eware of oscillations due to the resulting hysteresis if cl_start_down cl_beta . the current scale parameter which regards to the position deviation enc_pos_dev is depicted in figure 16 . 6 . for evaluating different upscaling and /or downscaling ramps the delay parameters cl_upscale_delay and cl_dnscale_delay can be used, too. these values define the clock cycles which are used to alter the current scale value for one step towards cl_i max resp. cl_imin . figure 16 . 7 depicts the c urrent scaling timing behavior as a function of cl_upsacle_delay and cl_dnscale_delay . figure 16 . 7 current s caling timing behavior 16.4.3 special parameters for abn encoders using closed loop c onsideration of b ack emf f or higher motor velocities and abn encoder s the load angle due to back emf can be compensated . therefore, set cl_emf_en = 1. the compensation angle no rmally does not exceed cl_beta , but for back emf error compensation another angle called gamma becomes added. thereby, the direction of movement is considered. the gamma value is greater than 0 if t he encoder velocity v_enc_mean exceeds cl_vmin_emf and g amma reaches its maximum value cl_gamma at v_enc_mean = cl_vmin_emf + cl_vadd_e mf as depicted in figure 16 . 8 . s c a l e _ p a r a m 0 c l _ i m i n x a c t u a l C c l _ s t a r t _ d o w n c l _ s t a r t _ d o w n C c l _ b e t a c l _ b e t a c l _ i m a x e n c _ p o s _ d e v [ s t e p s ] 1 2 8 ( 4 5 ) 2 5 6 ( 9 0 ) 3 8 4 ( 1 3 5 ) - 1 2 8 ( - 4 5 ) - 2 5 6 ( - 9 0 ) - 3 8 4 ( - 1 3 5 ) C c l _ s t a r t _ u p c l _ s t a r t _ u p t 0 a c t u a l c u r r e n t s c a l e t a r g e t v a l u e a c t u a l c u r r e n t s c a l e v a l u e c l _ u p s c a l e _ d e l a y = 0 c l _ u p s c a l e _ d e l a y > 0 c l _ d n s c a l e _ d e l a y > 0 c l _ d n s c a l e _ d e l a y = 0 c l _ i m a x c l _ i m i n s c a l e _ p a r a m
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 76 www.trinamic.com figure 16 . 8 calculation of the current loa d angle cl_gamma s ettings for v elocity r ead o ut v_enc the current encoder velocity v_enc is calculated with every ab transition. if no ab transitions have been recognized for enc_vel_zero clock cycles, v_enc is assigned to 0 and the enc_vel0 event becomes triggered, assumed that the v_enc value has not been zero before. note: v_enc is always set to zero with absolute encoders. v_enc_mean current filtered encoder velocity . this parameter is calculated every enc_vmean_wait clock cycles with the filter expon ent enc_vmean_filter . the parameter v_enc_mean is crucial for cl_gamma . it is calculated as follows: ? ?? ? ???? = ? ?? ? ???? ? ? ?? ? ???? 2 ??? _ ????? _ ?????? ? + ? ??? 2 ??? _ ????? _ ?????? ? enc_vel_zero delay time after the last incremental encoder value change. after enc_vel_zero clock c ycles v_enc _mean is set to zero. enc_vmean_wait set t his time period [clock cycles] to choose a delay before the next current encoder velocity value becomes considered for v_enc_mean calculation. it is recommend to set enc_vmean_wait to a higher value tha n 16! enc_velo event becomes triggered : encoder velocity has reached zero. h int a good starting value for enc_vmean_wait is 128 and for enc_vmean_filter is 7. both should be adapted in conjunction if abn encoder are used. further on, the lower both value s are the faster the v_enc_mean is adapted to the current velocity. but this also results in higher gradients of the mean velocity which could lead to regulation jumps if the gamma correction is enabled. to prevent this, check the v_enc_mean velocity value s during motion transferring the velocity limits cl_vmin_emf and (cl_vmin_emf + cl_vadd_emf). if the mean encoder velocity is adapted smoothly during motion gamma correction will be also executed properly. g a m m a u s u a l l y 2 5 5 ( = 9 0 ) v _ e n c _ m e a n c l _ v m i n _ e m f c l _ v a d d _ e m f c l _ g a m m a
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 77 www.trinamic.com 16.5 compensation of encoder misalignments a deficie ntly installed encoder can send values which do not result in a circle. often, the deviation from the real position results in a new function which is similar to a sine function. adding offset that follows a triangular shape can improve the encoder value e valuation significantly (refer to figure 16 . 9 ). figure 16 . 9 implemented triangular function to compensate for encoder misalignments the left graph illustrates the difference between encoder position and real position as a step function within the encoder resolution. after error compensation the position differences are minimized significantly as shown on the right side. for error compensation, the following triangular func tion has to be calculated and ma pped to the deviation function a s offset : ampl C enc_comp_ampl ; x off C enc_comp_xoffset ; y off C enc_comp_yoffset parameter description enc_comp_ampl defines the maximum amplitude of the offset function. enc_comp_xoffset define starting point s of the offset function . enc_comp_yoffset - 8 - 6 - 4 - 2 0 2 4 6 8 10 0 50 100 150 200 250 positi on deviation steps position deviation compensation function x off y off ampl - 2,5 - 2 - 1,5 - 1 - 0,5 0 0,5 1 1,5 2 0 50 100 150 200 250 positi on deviation steps position deviation
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 78 www.trinamic.com 17 serial encoder output unit the TMC4361 provides the possibility to render any regular encoder data into absolute ssi encoder data. the absolute ssi data is forwarded using the o utput pins which are used as normal spi output otherwise . p ins and r egisters : s erial e ncoder o utput u nit pin names type remarks nscsdrv_sdo output serial data output sckdrv_nsdo output negated serial data output sdodrv_sclk in /o ut as input serial clock input sdidrv_nsclk input negated serial clock input register name register address remarks general_conf 0x00 rw bit25 ? 24 ssi_out_mtime 0x04 rw bit24 ? 4 monoflop time of serial encoder output enc_in_conf 0x07 rw bit15 ? 14, bit30 enc_out_data 0x09 rw nu mber of data bits for encoder output structure enc_out_res 0x55 w resolution of the singleturn data for encoder output 17.1 providing ssi output d ata for providing ssi output data the following steps and considerations have to be made: - generally, the internal enc_pos is transferred into ssi output data. the structure of the output data can be altered freely to match master requirements. - for switching from spi output to ssi output, set serial_enc_out_enable to 1 . now, the master clock input sdo_drv_sclk s witche s to ssi protocol requirements . thereafter, nscsdrv_sdo act s as serial data output and send s data . - due to the regular differential ssi protocol the particular negated ports are sckdrv_nsdo for data output and sdi_drv_nsclk for clock input. the evaluation o f the differential clock input is based on the digital input levels. if serial_enc_out_diff_disable is set to 1 , ssi is supported withou t differential pairs of data input and clock output. - if multi_turn_out_en is set to 1 , the output data consists of multi turn and singleturn data. m ultiturn data is expressed as a signed number . - if multi_turn_out_en is set to 0 , only single turn data ( the angle as microsteps within one revolution ) is transferred. the resolution for singleturn data can be set with enc_out_ res . the internal enc_pos parameter becomes matched to this resolution . - set t he number of the single - and multiturn data with single_turn_res_out resp. multi_turn_res_out . the real number of data bits is the given parameter setting + 1 (see figure 17 . 1 ) . - additionally, the complete data can be gray coded by setting enc_out_gray to 1. - a fter the last master request transferred data remain s unchanged until ssi_out_mtime clock cycles are expired to support multi cycle data transfers. figure 17 . 1 example for ssi output configuration m: mulit_turn_res_out = 4 ? transfer of 5 multiturn data bits s: single_turn_res_out = 6 ? transfer of 7 singleturn data bits s e r i a l d a t a o u t s e r i a l c l o c k i n m s b m l s b m m s b s l s b s
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 79 www.trinamic.com 18 clk g ating if TMC4361 is not used for a while, clock gating can be used to reduce power consumption. p ins and r egisters : clk g ating pin names type remarks nscs_in input wakeup signal clk_ext input input pin of external clock generator register name register address remarks general _conf 0x00 rw bit18 ? 17 clk_gating_delay 0x14 rw delay time before clock gating is enabled clk_gating_reg 0x4f rw enable t rigger for clock gating by setting bit2 ? 0 to 111. 18.1 clock gating and wake - up c onfiguration for c lock g ating 1. to enable clock gating set clk_gating_en to 1. 2. now, clock gating becomes active as soon as clk_gating_reg is set to 111. 3. for a delay time between setting the register and starting the clock gating itself, clk_gating_delay can be set accordingly . the delay is given in clock cycles. 4. immediately after the start of the clk_gating_delay timer a sleep_timer event is triggered to indicate a soon clock gating phase. h int clock gating affect s every unit except the spi input unit, the timing unit , and essential registers for freeze process es , which are fed directly by the external clock. a utomatic c lock g ating it is possible to use automatic clock gating. therefore, set clk_gating_stdby_en to 1. after the TMC4361 has reached the standby state clock gating becomes enabled assumed that clk_ga ting_delay is set to 0. else, clock gating becomes started immediately after the clock gating timer expires. w ake - up p rocedure there are three possibilities for wake - up: - to wake up from clock gating nscs_in has to s witch to the active low level. - the w ake - up process can be automate d by using the internal start signal for ramp initialization. so, s hortly before the ramp start s , clock gating is cancelled for loading the essential registers for start ing the ramp properly. - e xternal start signals can also be u sed to finish clock gating. figure 18 . 1 shows the process of manual clock gating ( due to setting the appropriate register) and manual wake up (by using the spi input lines) including different clock gating delays. first the clock gating timer has to expire and then the second phase of clock gating starts. figure 18 . 1 manual clock gating and manual wake up. e x t e r n a l c l k s i g n a l i n t e r n a l c l k s i g n a l c l k _ g a t i n g _ r e g = 1 1 1 c l k _ g a t i n g _ d e l a y = 5 c l k _ g a t i n g _ r e g = 1 1 1 s p i i n p u t s c l o c k g a t i n g d e l a y t i m e r
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 80 www.trinamic.com figure 18 . 2 de picts a complete automatic clock gating transition from inactive to active and back. here, automatic clock gating is realized using the internal standby status (active high level at stdby_clk output) and the internal start timer. clock gating ends slightly before the start signal becomes active. thus, essential registers can be loaded before ramp start. figure 18 . 2 automatic clock gating h int note that manual and automated clock gating transition can be used together. e x t e r n a l c l k s i g n a l i n t e r n a l c l k s i g n a l s t d b y _ c l k o u t p u t i n t e r n a l s t a r t t i m e r i n t e r n a l c l o c k g a t i n g t i m e r
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 81 www.trinamic.com 19 register s and switches changes as regards TMC4361old are displayed in green letters. 19.1 general configuration g enera l configuration (0 x 00 ) r/w addr reg name bit description rw 0x00 general_conf default: 0x 00006020 0 use_astart_and_vst art (only valid for s - shaped ramps) 0 if vstart 0, aactual will be set to amax or - amax 1 if vstart 0, aactual will be set to astart or - astart 1 direct_acc_val_en 0 acceleration values are divided by clk_freq 1 acceleration values are set directly as steps per clock cycle 2 direct_bow_ val_en 0 bow values are calculated due to division by clk_freq 1 bow values are set directly as steps per clock cycle 3 step_inactive_pol 0 stpout=1 indicates an active step 1 stpout=0 indicates an active step 4 toggle_step 0 only stpout trans itions from inactive to active polarity indicate steps 1 every level change of stpout indicates a step 5 pol_dir_out 0 dirout = 0 indicates negative direction 1 dirout = 1 indicates negative direction 7:6 sdin_mode 00 internal step control (inte rnal ramp generator will be used) 01 external step control (stpin/dirin) with high active steps 10 external step control (stpin/dirin) with low active steps 11 external step control (stpin/dirin) with toggling stpin input signals 8 pol_dir_in 0 diri n = 0 indicates negative direction 1 dirin = 1 indicates negative direction 9 sd_indirect_control 0 stpin/dirin input signals will manipulate steps directly 1 stpin/dirin input signals will manipulate xtarget register value, internal ramp generator u sage despite sdin_mode 0 11 : 10 serial_enc_in_mode 00 incremental encoder connected to encoder interface 01 absolute ssi encoder connected to encoder interface 10 reserved (prohibited to use!) 11 absolute spi encoder connected to encoder interface 12 diff_enc_in_disable 0 differential encoder interface inputs enabled 1 differential encoder interface inputs disabled (automatically for spi encoder) 14 : 13 stdby_clk_pin_assignment 00 standby signal becomes forwarded with an active low level 01 standby signal becomes forwarded with an active high level 10 stdby_clk passes chopsync clock (tmc23x, tmc24x only) 11 internal clock is forwarded to stdby_clk output pin 15 intr_pol 0 intr =0 indicates an active interrupt 1 intr =1 indicates an active interrupt
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 82 www.trinamic.com g enera l configuration (0 x 00 ) r/w addr reg name bit description 16 invert_pol_target_reached 0 target_reached signal set to 1 indicates target reached event 1 target_reached signal set to 0 indicates target reached event 17 clk_gating_en 0 no clock gating. 1 internal clock is gated due to c lock gating register. a delay until sleep is possible (see clock gating timer register). wakeup is possible due to active nscsin or if a start signal (internal or external) is generated. 18 clk_gating_stdby_en 0 no clock gating due to standby phase . 1 internal clock is gated due to standby of motion controller. 19 fs_en 0 no fullsteps. 1 spi output forwards fullsteps, if | vactual | > fs_vel (TMC4361 calculates internally with the step resolution) 20 fs_sdout 0 no fullsteps for step/dir o utput. 1 fullsteps are forwarded via step/dir output also. 22:21 dcstep_mode 00 dcstep is disabled 01 dcstep signal generation will be selected automatically 10 dcstep with external step_ready signal generation ( tmc21xx/51xx ) 11 dcstep with interna l step_ready signal generation (tmc26x) tmc26x config: use const_toff - chopper (chm = 1), slow decay only (hstrrt = 0) and tst = 1 and sgt0=sgt1=1 (on_state_xy) 23 pwm_out_en 0 pwm output disabled (step/dir out). 1 stpout/dirout used as pwm output (p wma/pwmb). 24 serial_enc_out_enable 0 no encoder connected to spi output. 1 spi output used as ssi encoder interface to pass out absolute ssi encoder data. 25 serial_enc_out_diff_disable 0 differentia l serial encoder output enabled or disabled (= 1) 26 automatic_direct_sdin_switch_off 0 vactual =0 & aactual =0 after switching off direct_sdin_mode 1 vactual = vstart and aactual = astart after switching off d irect_sdin_mode 27 circular_cnt_as_xlatch 0 x_latch will be forwarded at 0x36 1 r ev_cnt (# of internal revolutions) will be forwarded at 0x36 28 reverse_motor_dir 0 direction of internal sinlut is regular 1 direction of internal sinlut will be reversed 29 intr_tr_pu_pd_en 0 intr and target_reached are only outputs 1 intr and target_reached will be used as outputs and with gated pull - up and/or pull - down functionality 30 intr_as_wired_and 0 intr output function could be used as wired - or 1 intr output function could be used as wired - and 31 tr_as_wired_and 0 target_reac hed output function could be used as wired - or 1 target_reached output function could be used as wired - and
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 83 www.trinamic.com 19.2 reference switch configuration r eference switch conf iguration (0 x 01 ) r/w addr reg name bit description rw 0x0 1 reference_conf default: 0x 0000 000 0 0 stop_left_en 0 stopl signal processing disabled. 1 stopl signal processing enabled. 1 stop_right_en 0 stopr signal processing disabled. 1 stopr signal processing enabled. 2 pol_stop_left 0 motor stops if stopl signal is 0. 1 motor stops if stop l signal is 1. 3 pol_stop_right 0 motor stops if stopr signal is 0. 1 motor stops if stopr signal is 1. 4 invert_stop_direction 0 stopl/stopr stop motor in negative/positive direction. 1 stopl/stopr stop motor in positive/negative direction. 5 soft_stop_en 0 hard stop enabled. vactual is immediately set to 0 on any external stop event. 1 soft stop enabled. a linear velocity ramp is used for decreasing vactual to v = 0. 6 virtual_left_limit_en 0 position limit virt_stop_left disabled. 1 position limit virt_stop_left enabled. 7 virtual_right_limit_en 0 position limit virt_stop_right disabled. 1 position limit virt_stop_right enabled. 9 : 8 virt_stop_mode 00 the current ramp type defines the deceleration ramp triggered by a virtual stop event (prohibited for s - shaped ramps!) . 01 vactual is set to 0 on a virtual stop event (hard stop) 10 soft stop is enabled with linear velocity ramp (from vactual to v = 0). 10 latch_x_on_inactive_l 0 no latch of xactual if stopl becomes inacti ve. 1 x_latch = xactual will be triggered if stopl becomes inactive. 11 latch_x_on_active_l 0 no latch of xactual if stopl becomes active. 1 x_latch = xactual will be triggered if stopl becomes active. 12 latch_x_on_inactive_r 0 no latch of xac tual if stopr becomes inactive. 1 x_latch = xactual will be triggered if stopr becomes inactive. 13 latch_x_on_active_r 0 no latch of xactual if stopr becomes active. 1 x_latch = xactual will be triggered if stopr becomes active. 14 stop_left_is _home 0 stopl input signal is not home position. 1 stopl input signal is also home position. 15 stop_right_is_home 0 stopr input signal is not home position. 1 stopr input signal is also home position.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 84 www.trinamic.com r eference switch conf iguration (0 x 01 ) r/w addr reg name bit description 19 : 16 home_event 0000 next active n signal of abn encoder signal indicates home position. 0011 home = 0 indicates negative region/position from home. 1100 home = 1 indicates negative region/position from home. 0110 home = 1 indicates an active home event C x_home is located in the middle of the active range. 0010 home = 1 indicates an active home event C x_home is located at the rising edge of the active range. 0100 home = 1 indicates an active home event C x_home is located at the falling edge of the active range. 1001 home = 0 indicates an a ctive home event C x_home is located in the middle of the active range. 1011 home = 0 indicates an active home event C x_home is located at the rising edge of the active range. 1101 home = 0 indicates an active home event C x_home is located at the falli ng edge of the active range. 20 start_home_tracking 0 no storage of x_home = xactual by passing home position. 1 storage of xactual as x_home at next regular home event. the switch will be reset after an executed homing. an xlatch_done event will be also released then. 21 clr_pos_at_target 0 ramp stops at xtarget if positioning mode is active. 1 set xactual = 0 after xtarget has been reached. the next ramp starts immediately. 22 circular_movement_en 0 range of xactual will not be limited 1 range of xactual will be limited to - x_range xactual ( x_range - 1) 24 : 23 pos_comp_output 00 target_reached is set active on target_reached event. 11 target_reached triggers on poscomp_reached event. 25 pos_comp_source 0 pos_comp is compared to internal position xactual . 1 pos_comp is compared with external position enc_pos. 26 stop_on_stall 0 motor will not be stopped in case of stall. 1 motor will be stopped with a hard stop in case of stall. 27 drv_after_stall set to 1 and reset stop_on_stall flag. moving the motor is not possible as long as this flag is not set after a stop_on_stall event. 29 : 28 modified_pos_compare: pos_comp_reached_f / event is based on comparison between xactual resp. enc_pos and 00 pos_comp 01 x_home 10 x_latch / enc_latch 11 rev_cnt 30 a utomatic_cover 0 spi output will not transfer automatically any cover datagram 1 spi output interface will send automatically cover datagrams when vactual cross es spi_switch_vel . 31 circular_enc_en 0 range of enc_pos will not be limited 1 range of enc_pos will be limited to - x_range enc_pos ( x_range - 1)
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 85 www.trinamic.com 19.3 start switch configuration s tart switch configuration (0 x 02 ) r/w addr reg name bit description rw 0x0 2 start_conf default: 0x 0000 000 0 4: 0 start_en xxxx1 c hange of xtarget requires a distinct start signal . xxx1x c hange of vm ax requires a distinct start signal . xx1xx c hange of rampmode requires a distinct start signal . x1xxx c hange of gear_ratio requires a distinct start signal . 1xxxx usage of shadow registers enabled. 8 : 5 trigger_events 0000 start signal generation is disabled. xxx0 start pin is assigned as outpu t. xxx1 external start signal is assigned as start signal for timer . xx1x target_reached event is assigned as start signal for timer . x1xx velocity_reached event is assigned as start signal for timer . 1xxx poscomp _reached event is assigned as start signal for timer . 9 pol_start_signal (same polarity for input or output) 0 start = 0 is active start polarity 1 start = 0 is inactive start polarity 10 immediate_start_in 0 a ctive start input starts internal start timer 1 a ctive start will be executed immediately 11 busy_state_en 0 start pin is used as input or output only 1 busy start state enabled: before the internal start is valid, start output will be set busy (strong inacti ve polarity). then, if the internal start signal is generated (after start timer is elapsed), the start signal is set to the active polarity (weak output driving strength). if the signal at the start input is set to the active polarity, e.g. because all me mbers at the signal line are ready, the start output remains active (strong driving strength) for start_out_add clock cycles. then, busy state is active again until the next start signal. 15:12 pipeline_en 0000 no pipeline is active. xxx1 x_target wi ll be considered for pipelining. xx1x pos_comp will be considered for pipelining. x1xx gear_ratio will be considered for pipelining. 1xxx general_conf will be considered for pipelining. 17:16 shadow_option 00 single - level shadow registers for 13 re levant ramp parameters 01 double - stage shadow register (appropriate for s - shaped ramps). 10 double - stage shadow register (ap propriate for trapezoidal ramps without vstop consideration). 11 double - stage shadow register (appropriate for trapezoidal ramps without vstart consideration). 18 cyclic_shadow_regs 0 current ramp parameters will not written back to the shadow regs 1 current ramp parameters will be written back to the appropriate shadow registers at the next internal start signal 19 syn chro_via_mp_pins 1 closed loop state of different TMC4361 could be coordinated by the usage of the multipurpose pins mp1 and mp2 23:20 shadow_miss_cnt: number of unused start signals between two consecutive shadow register transfers 31:24 xpipe_re write_reg indicates which x_pipex register becomes changed to x_target value on next internal start event and if x_pipeline_en 0 .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 86 www.trinamic.com 19.4 input filter configuration i nput filter configur ation (0 x 03 ) r/w addr reg name bit description rw 0x03 input_filt_conf default: 0x00000000 2 : 0 sr_enc_in input sample rate = f clk / 2 sr_enc_in for a_sclk, aneg_nsclk, b_sdi, bneg_nsdi, n, and nneg 3 reserved. set to 0. 6 : 4 filt_l_enc_in # a dditional ly sampled input bits whose voltage level has to be equal to the recen tly sampled bit to provide a valid input bit level for a_sclk, aneg_nsclk, b_sdi, bneg_nsdi, n, and nneg . 7 sd_filt0: selection bit to assign sd input interface pins (stpin, dirin) to the _enc_in input filter group. 10 : 8 sr_ref input sample rate = f clk / 2 sr_ref for stopr, home_ref, and stopl . 11 reserved. set to 0 . 14 : 12 filt_l_ref # a dditional ly sampled inp ut bits whose voltage level has to be equal to the recently sampled bit to provide a valid input bit level for stopr, home_ref, and stopl . 15 sd_filt1: selection bit to assign sd input interface pins (stpin, dirin) to the _ref input filter group. 18 : 16 sr_s input sample r ate = f clk / 2 sr_s for start . 19 reserved. set to 0 . 22 : 20 filt_l_s # a dditional ly sampled in put bi ts whose voltage level has to be equal to the recently sampled bit to provide a valid input bit level for start . 23 sd_filt2: selection bit to assign sd input interface pins (stpin, dirin) to the _s input filter group. 26 : 24 sr_enc_out input sampl e r ate = f clk / 2 sr_enc_out for sdodrv_sclk, and sdidrv_nsclk. 27 reserved. set to 0 . 30 : 28 filt_l_enc_out # a dditional ly sampled inp ut bits whose voltage level has to be equal with the recently sampled bit to provide a valid input bit level for sdodrv_sclk, and sdidrv_nsclk 31 sd_filt3: selection bit to assign sd input interface pins (stpin, dirin) to the _enc_out input filter group.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 87 www.trinamic.com 19.5 s pi - out configuration spi - o ut configuration (0 x 0 4 ) r/w addr reg name bit description rw 0x0 4 spiout_con f default: 0x 0000 000 0 b asic spi - o ut s ettings 3 : 0 spi_output_format 0000 spi - out off 1000 spi - out connected to tmc23x driver 1001 spi - out connected to tmc24x driver 1010 spi - out connected to tmc26x/389 1011 spi - out connected to tmc26x/389. s teps on ly via stpout . 1100 spi - out connected to tmc21xx/51xx . s teps only via stpout . 1101 spi - out connected to tmc21xx/51xx . 0100 t he actual unsigned scaling factor is assigned to spi - out . 0101 both actual signed sinlut value s are assigned to spi - out . 0110 t he actual unsigned scaling factor is merged with dac_addr_a as output for a spi - dac. 0010 spi - out is connected with a dac. absolute values. p hase of coila via stpout. p hase of coilb via diro ut. phase bit = 0 : positive val ues. 0011 spi - out is connect ed with a dac. absolute values. p hase of coila via stpout . phase of coilb via dirout. phase bit = 1 : positive val ues. 0001 spi - out is connected with a dac. v alues are mapped. current = 0 : vdd/2 current = - ( max _value) : 0 c urrent = max _valu e : vdd 1111 only spi cover datagrams will be transferred 19 : 13 cover_data_length ( 064 ) set to 0 for automatic assign, if a tmc driver is connected. otherwise it will set to 1 if cover_data_length = 0 and no tmc driver is selected . 23 : 20 spi_ out_low_time spi - out put clock low phase [ cl oc k cycles ] 27 : 24 spi_out_high_time spi - out put clock high phase [ cl oc k cycles ] 31 : 28 spi_out_block_time spi - out put blockage time [ cl oc k cycles ] s ettings used with se rial encoder output only : serial _enc_out_enable = 1 23 : 4 ssi_out_mtime ssi output monoflop time: delay time during which the absolute data remain stable after the last master request. [ cl oc k cycles ]
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 88 www.trinamic.com spi - o ut configuration (0 x 04 ) r/w addr reg name bit description s ettings used with tmc23 x /24 x motor driver s only : spi_output_format (3 : 1) = b 100 5 : 4 mixed_decay (coila and coilb for a tmc23x or tmc24x driver) 00 b oth mixed decay bits are always off . 01 d uring falling ramp s until reaching the value of 0 m ixed decay bits are o n . 10 b oth m ixed decay bits are alway s on, except standby mode is active. 11 b oth mixed decay bits are always on . 6 stdby_on_stall_for_24x (tmc24x only) 0 n o standby datagram . 1 in case of a stop_on_stall event a standby datagram is sent to the tmc 24x driver . 7 stall_flag_instead_of_uv_en (tmc24x only) 0 u ndervoltage flag is forwarded as status (24) . 1 c alculated stall status of tmc24x is forwarded as status (24). 10 : 8 stall_load_limit (tmc24x only) a stall is detected if stall_load_limit (ld2&ld1&ld0) of the driver status . 11 pwm_phase_shft_enable 0 no phase shift during pwm mode. 1 during pwm mode the internal sinlut microstep position will be shifted for ms_offset microsteps to shift the sine/cosine values for a phase shift of ( ms_offset / 1024 ? 360) s ettings used with tmc26 xx /21 xx motor driver only : spi_output_format = b 101x or b 110x 4 three_phase_stepper_en (tmc26x/389 only) 0 a 2 - phase stepper driver is connected (tmc26x) 1 a 3 - phase stepper driver is connected (tmc389) 5 scale_val_transfer_en 0 no transfer of scale values to the tmc driver . 1 transfer of current scale values to the correct driver registers . 6 disable_polling 0 p ermanent transfer of datagrams to check driver status (s tep /d ir o ut put only ) 1 n o tr ansfer of polling datagrams . (recommended for spi_output_format = b 1101 ) 12 : 7 poll_block_mult m ultiplier for calculating the time interval betwee n consecutive polling datagrams. t poll = ( poll_block_mult +1) ? spi_out_block_time / f clk s ettings us ed with motor driver s from third parties : spi_output_format (3) = 0 4 sck_low_before_csn 0 nscsdrv_sdo tied low before sckdrv_nsdo 1 sckdrv_nsdo tied low before nscsdrv_sdo 5 new_out_bit_at_rise 0 sdodrv_sclk is shifted at falling edge of sckdrv _nsdo . 1 sdodrv_sclk is shifted at rising edge of sckdrv_nsdo . 11 : 7 dac_cmd_length # of bits for command address if spi_output_format = b000 1 or b 0010 or b 0011 or b 0110 .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 89 www.trinamic.com 19.6 current configuration c urrent configuration (0 x 0 5 ) r/w addr reg name bit description rw 0x05 current_conf default: 0x 0000 000 0 0 hold_current_scale_en 0 n o hold current scaling during standby phase . 1 h old current scaling during standby phase . 1 drive_current_scale_en 0 n o drive current scaling during motion . 1 d rive c urrent scaling during motion . 2 boost_current_on_acc_en 0 n o boost current scaling for acceleration ramps . 1 b oost current scaling if ramp_state = b 01 . 3 boost_current_on_dec_en 0 n o boost current scaling for deceleration ramps . 1 b oost current scaling if ramp_state = b 10 . 4 boost_current_after_start_en 0 n o boost current at ramp start . 1 t emporary boost current if vactual = 0 and new ramp start s. 5 sec_drive_current_scale_en 0 o ne drive current value for the whole motion ramp . 1 s ec ond drive current scaling for vactual > vdrv_scale_limit . 6 freewheeling_en 0 n o freewheeling . 1 f reewheeling after standby phase . 7 closed_loop_scale_en 0 n o closed loop current scaling . 1 c losed loop current scaling : sets current_conf ( 6 : 0 ) = 0 turn off for closed loop calibration with maximum current! 8 pwm_scale_reg_chn 0 pwm_ampl value will be taken from register 0x06(15:0). 1 pwm_ampl value will be taken from register 0x05(31:16). 15:9 reserved. set to b0000000. 31 :16 pwm_amp l if pwm_scale_reg_chn = 1 19.7 current scale values c urrent scale values (0 x 06 ) r/w addr reg name bit description rw 0x06 scale_values default: 0xffffffff 7 : 0 boost_scale_val : o pen loop boost scaling value . cl_imin : closed loop minimum scaling value . 15 : 8 drv1_scale_val : o pen loop first drive scaling value . cl_imax : closed loop maximum scaling value . 23 : 16 drv2_scale_val : o pen loop second drive scaling value . cl_start_up : | enc_pos_dev | value at which closed loop scaling increase s the current scaling value above cl_imin . 31 : 24 hold_scale_val : o pen loop standby scaling value . cl_start_down : | enc_pos_dev | value at which closed loop scaling decrease s the current scaling value below cl_imax . if set to 0 it is automatically equal to cl_beta . 15 : 0 pwm_ampl : pwm amplitude at vactual = 0. maximum duty cycle = (0.5 + ( pwm_ampl + 1) / 2 17 ) minimum duty cycle = (0.5 C ( pwm_ampl + 1) / 2 17 ) pwm_ampl = 2 16 C 1 at vactual = pwm_vmax use following scale values: real scaling value = (x +1) / 32 i f spi_output_format = b 1011 or b 1100 = (x+1) / 256 any other spi_output_format setting
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 90 www.trinamic.com 19.8 encoder signal configuration e ncoder signal config uration (0 x 07 ) r/w addr reg name bit description rw 0x07 enc_in_conf default: 0x 00000400 0 enc_se l_decimal 0 e ncoder constant represent s a binary number . 1 e ncoder constant represent s a decimal number (for abn only) . 1 clear_on_n 0 enc_pos is not re set at active n events. 1 enc_pos is set to 0 or enc_reset_val on every n event. do not use for c losed loop operation ! enc_in_conf(2) or enc_in_conf(3) have to be set! 2 clr_latch_cont_on_n 1 value of enc_pos is cleared and/or latched to enc_latch register on every n event. 3 clr_latch_once_on_n 1 v alue of enc_pos is cleared and/or latched t o enc_latch register on the next n event. this bit is set to 0 after latching/clearing once. 4 pol_n 0 active polarity for n event is low level. 1 active polarity for n event is high level. 6 : 5 n_chan_sensitivity 00 n event is active as long as n is active. 01 n event triggers when n becomes active (positive edge) . 10 n event triggers when n becomes inactive (negative edge) 11 n event triggers when n becomes active or inactive (both edges) 7 pol_a_for_n 0 a polarity has to be low for a v alid n event . 1 a polarity has to be high for a valid n event . 8 pol_b_for_n 0 b polarity has to be low for a valid n event 1 b polarity has to be high for a valid n event 9 ignore_ab 0 consider a and b polarities for a valid n event . 1 ignore p olarities of a and b signals for a valid n event. 10 latch_enc_on_n 0 no latch of enc_pos on an active n event 1 enc_latch = enc_pos triggered on an active n event enc_in_conf(2) or enc_in_conf(3) have to be set! 11 latch_x_on_n 0 do not latch xa ctual on active n event . 1 x_latch = xactual triggered on an active n event . 12 multi_turn_in_en 0 s erial encoder input transmit s singleturn values . 1 s erial encoder input transmit s singleturn and multiturn values . 13 multi_turn_in_signed 0 m ultiturn values from serial encoder input are unsigned numbers . 1 m ultiturn values from serial encoder input are signed numbers . 14 multi_turn_out_en 0 s erial encoder output transmit s singleturn values . 1 s erial encoder output transmit s singleturn a nd multiturn values . 15 use_usteps_instead_of_xrange 0 x_range is also valid if circular movement is used for encoders 1 usteps_per_rev is valid if circular movement is used for encoders 16 calc_multi_turn_behav 0 no multiturn calculation. 1 multiturn calculation for singleturn encoder data.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 91 www.trinamic.com e ncoder signal config uration (0 x 07 ) r/w addr reg name bit description 17 ssi_multi_cycle_data 0 e very absolute ssi value request is executed once . 1 e very absolute ssi value request is executed twice . 18 ssi_gray_code_en : ssi input data is binary coded (=0) or gray coded (=1). 19 left_aligned_data 0 s erial input data is aligned right (first flags, then data) . 1 s erial input data is aligned left (first data, then flags) . 20 spi_data_on_cs (spi encoder only (serial_enc_in_mode = b11)) 0 bneg_nsdi will pro vide output data at next a_sclk transition 1 bneg_nsdi will provide output data immediately if aneg_nsclk input signal level is tied low transition 21 spi_low_before_cs (spi encoder only (serial_enc_in_mode = b11)) 0 a_sclk will tied low after aneg _nsclk switches to low level 1 a_sclk will tied low before aneg_nsclk switches to low level 23 : 22 regulation_modus 00 n o feedback consideration . 01 c losed loop operation . 10 pid regulat ion. pulse generator base is zero. 11 pid regulation . pulse ge nerator base is vactual . 24 cl_calibration_en 0 n o closed loop calibration . 1 c losed loop calibration is active . use maximum current without scaling during calibration! the motor driver should be positioned at a fullstep posi tion and vactual has to be set to 0 during the calibration process ! 25 cl_emf_en 0 do not consider back emf during closed loop operation . 1 closed loop operation considers back emf if vactual > cl_vmin . 26 cl_clr_xact 0 enc_pos_dev will not evaluated to manipulate x_a ctual 1 xactual = enc_pos , if enc_pos_dev > enc_pos_dev_tol 27 cl_vlimit_en 0 n o maximum velocity limit for closed loop regulation . 1 pi maximum velocity regulation during closed loop operation . 28 cl_velocity_mode_en 0 no limit for difference b etween xactual and enc_pos 1 difference between xactual and enc_pos is limited to cl_offset + 768 steps (+3 fullsteps @ 256 steps/fs) . if the limit is exceeded xactual will be set accordingly. 29 invert_enc_dir : set this parameter to 1 for inverting the enc_pos value . 30 enc_out_gray: ssi output data is binary coded (=0) or gray coded (=1). 31 no_enc_vel_preproc = 0 ab signal is preprocessed for encoder velocity (could only be used with serial_enc_in_mode = b00). set no_enc_vel_preproc to 1 to end ab signal preprocessing. serial_enc_variation_limit = 1 two consecutive seria l encoder values must no vary more than one eighth of the encoder re solution enc_in_res to be valid. this setting can only be used with serial_enc_in_mode 0.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 92 www.trinamic.com 19.9 seri al encoder data in s erial encoder data in (0 x 08 ) r/w addr reg name bit description rw 0x08 enc_in_data default: 0x 0000 000 0 4 : 0 single_turn_res # data bits for angle within one revolution = single_turn_res + 1 . 9 : 5 multi_turn_res # data bits for revo lut ion count = multi _turn_res + 1. if multi _turn_res = 0, no data bits will be expected. 11 : 10 status_bit_cnt : # bits of status data 15 : 12 crc_bit_cnt : l ength of crc polynom ial (#bits) 23 : 16 serial_addr_bits # bits for addresses within spi d atagram / biss frame . 31 : 24 serial_d ata_bits # bits for data within spi datagram / biss frame . 19.10 serial encoder data out s erial encoder data out (0 x 09 ) r/w addr reg name bit description rw 0x09 enc_out_data default: 0x 0000 000 0 4 : 0 single_turn_res_out : # data bits for angle within one revolution = single_turn_res_out + 1 . 9 : 5 multi_turn_res_out # data bits for revolution count = multi_turn_res_out + 1 . 31 : 10 reserved. set all bits to 0 . 19.11 motor d river settings m otor driver settings (0 x 0a ) r/ w addr reg name bit description rw 0x0a step_conf default: 0x 00 fb 0 c 80 3 : 0 mstep_per_fs b 0000 highest step resolution: 256 steps per fullstep. b0001 b0111 128 steps half steps b 1000 full steps (maximum possible setting) note: - set to 256 f or closed loop operation. - when using a s tep /d ir driver, it must be capable of a 256 resolution via s tep /d ir input for best performance (but lower resolution s tep /d ir drivers can be used as well ) . 15 : 4 fs_per_rev : fullsteps per revolution 23 : 16 mst atus_selection : ored with motor driver status register set (7 ? 0) ? if set here & particular flag is set, an event will be generated at events(30) 31 : 24 reserved: set to b00000000 19.12 event selection r egisters e vent selection r/w addr reg name bit descr iption rw 0x0 b spi_status_selection default: 0x 82029805 31 : 0 ev ents which bits are selected (=1 ) in this register are forwarded to the eight status bits that are transferred with every spi datagram (first eight bits from lsb are significant!) . 0x0c eve nt_clear_conf default: 0x 0000 000 0 31 : 0 events which bits are selected (= 1 ) in this register are not cleared by reading out the events register 0x 0e . 0x0d intr_conf default: 0x 0000 000 0 31 : 0 ored with interrupt event r egister s et : if set here and the part icular flag is set an interrupt becomes generated .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 93 www.trinamic.com 19.13 status event register s tatus events (0 x 0e ) r/w addr reg name bit description r+c 0x0e events default: 0x 0000 000 0 0 target_reached has been triggered . 1 pos_comp_reached has been triggered . 2 v el_reached has been triggered . 3 vel_state = b 00 has been triggered ( vactual = 0) . 4 vel_state = b 01 has been triggered ( vactual > 0) . 5 vel_state = b 10 has been triggered ( vactual < 0) . 6 ramp_state = b 00 has been triggered ( aactual = 0) . 7 ramp_state = b 01 has been triggered ( | aactual | increases ) . 8 ramp_state = b 10 has been triggered ( | aactual | de creases ) . 9 max_phase_trap : trapezoidal ramp has reached its limit speed using maximum values for amax and dmax for accelerati on /deceleration ( vactual > vbreak ; vbreak 0) . 10 frozen : nfreeze has been tied low . reset TMC4361 for further motion! 11 stopl has been triggered. m ovement in negative direction is not executed until this event is cleared and ( stopl is not active any more or stop_left_en is set to 0 ) . 12 stop r has been triggered. m ovement in positive direction is not executed until this event is cleared and ( stopr is not active any more or stop_ right _en is set to 0) . 13 vstopl_active : vstopl has been activ ated. no further movement in negative direction until this event is cleared and ( a new value is chosen for vstopl or x_actual or set virtual_left_limit_en = 0) . 14 vstopr_active : vstop r has been activated. no further movement in positive direction unti l this event is cleared and (a new value is chosen for vstop r or x_actual or set virtual_ right _limit_en = 0). 15 home_error : home_ref has wrong polarity and is outside of safety margin around x_home . 16 xlatch_done : indicates if x_ latch or x_home h as been newly written. 17 fs_active : ful lstep has been activated. 18 enc_fail : mismatch between xactual and enc_pos has been triggered . 19 n_active : active n event has been triggered . 20 enc_done indicates if enc_latch has been newly writte n. 21 ser_enc_data_fail : failure during multi cycle data evaluation or between two consecutive data requests . 22 reserved 23 ser_data_done : data has been received from serial encoder (spi, biss). 24 one of the s erial_enc_flags has been set . 25 cover_done : spi datagram have been sent to the motor driver. 26 enc_vel0 : encoder velocity has been reached 0 . 27 cl_max : closed loop commutation angle has reached maximum value . 28 cl_fit : cl_fit_f has been triggered . 29 stop_on_s tall : motor stall detected. motor has been stopped. 30 motor_ev : one of the chosen tmc motor driver flags has been triggered. 31 rst has been activated. (divergence to TMC4361old where sleep_timer event has been reported here ) .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 94 www.trinamic.com 19.14 status flag reg ister s tatus flags (0 x 0f ) r/w addr reg name bit description r 0x0f status default: 0x 0000 000 0 0 target_reached_f is set high if xactual = xtarget 1 pos_comp_reached_f is set high if xactual = pos_comp 2 vel_reached_f is set high if vactual = a bs( vmax ) 4 : 3 vel_state_f : current velocity state: 00 vactual = 0 01 vactual > 0 10 vactual < 0 6 : 5 ramp_state_f : current ramp s tate. 00 aactual = 0 01 acceleration phase: aactual > 0 if vactual > 0 or aactual < 0 if vactual < 0 10 deceleration phase: aactual < 0 if vactual > 0 or aactual > 0 if vactual < 0 7 stopl_active_f : left stop switch is active . 8 stopr_active_f : right stop switch is active . 9 vstopl_active_f : left virtual stop switch is active . 10 vst opr_active_f : right virtual stop switch is active . 11 active_stall_f : m otor stall is detected and vactual > vstall_limit . 12 home_error_f home_ref input signal level is not equal to the expected home level 13 fs_active_f : fullstep operation is active. 14 enc_fail_f : m ismatch between xactual and enc_pos is out of tolerated range enc_pos_dev_tol . 15 n_active_f : n event is active . 16 enc_latch_f : enc_latch is newly written . 17 multi_cycle_fail _f ( serial_enc_in_ mode 00) : indicates a failure during last multi cycle data evaluation . ser_enc_var_f ( serial_enc_in_ mode 00 ): indicates a f ailure during last serial data evaluation due to a substantial deviation between two consecuti ve serial data values ( serial_enc_variat ion_limit = 1 ) . the variation is bigger than one eighth of enc_in_res . 18 reserved 19 cl_fit_f : active if enc_pos_dev < cl_tolerance . the c urrent mismatch between xactual and enc_pos is within tolerated range . 23 : 20 s erial_enc_flags : fl ags r eceived from serial encoder. these flags are reset with a new encoder transfe r request . 24 sg : stallguard2 status (rcvd from tmc26x / tmc21xx/51xx motor driver) or s tall guard status ( calculated for tmc24x) . uv_sf : u ndervoltage flag (rcvd from tmc23x / tmc24x motor driver). 25 ot : overtemperature shutdown (rcvd from any tmc motor driver). 26 otpw : overtemperature warning (rcvd from any tmc motor driver). 27 s2ga : short to ground detection bit for high side mosfet of coil a (rcvd from tmc26x / tmc21xx/51xx motor driver). oca : overcurrent b ridge a (rcvd from tmc23x / tmc24x motor driver). 28 s2gb : short to ground detection bit for high side mosfet of coil b (rcvd from tmc26x / tmc21xx/51xx motor driver). ocb : overcurrent b ridge b (rcvd from tmc23x / tmc24x motor driver). 29 ola : open load indicator of coil a (rcvd from any tmc motor driver). 30 olb : open load indicator of coil b (rcvd from any tmc motor driver). 31 stst : standstill indicator (rcvd from tmc26x / tmc21xx/51xx motor driver). ochs : overcurrent high sid e (rcvd from tmc23x / tmc24x motor driver).
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 95 www.trinamic.com 19.15 various configuration registers v arious c onfiguration registe rs : closed loop , switches r/w addr reg name (default) s/u bit description rw 0x10 stp_length_add (0x0000) u 15 : 0 additional length [# cl oc k cycles] for active step polarity to indicate an active output step at stpout dir_setup_time (0x0000) 31 : 16 delay [ # cl oc k cycles] between dirout and stpout voltage level ch anges. 0x11 start_out_add (0x00000000) u 31 : 0 additional length [# cl oc k cycles] for active start signal. a ctive start signal length = 1+start_out_add 0x12 gear_ratio (0x01000000) s 31:0 constant value which will be added to internal position counter w ith every active step at stpin value representation: 8 digits and 24 decimal places. 0x13 start_delay (0x00000000) u 31 : 0 delay time [# cl oc k cycles] between start trigger and internal start signal release. 0x14 clk_gating_delay (0x00000000) u 31 : 0 d elay time [# cl oc k cycles] between trigger and initialization of an active clock gating. 0x15 stdby_delay (0x00000000) u 31 : 0 delay time [# cl oc k cycles] after a ramp end before activating the standby phase. 0x16 freewheel_delay (0x00000000) u 31 : 0 del ay time [# cl oc k cycles] between initialization of an active standby phase and freewheeling initialization. 0x17 vdrv_scale_limit (0x00000000) u 23 : 0 drive scaling limit: drv2_scale_val is active if vactual > vdrv _ scale_limit , else drv1_scale pwm_vma x (0x00000000) pwm: velocity value at which the scaled pwm value reaches the maximum scale parameter 1. 0x18 up_scale_delay (0x000000) u 23 : 0 increment delay [# cl oc k cycles]. the value defines the clock cycles which are used to increase the current sc ale value for one step towards higher values. cl_upscale_delay (0x000000) increment delay [# cl oc k cycles]. the value defines the clock cycles which are used to increase the current scale value for one step towards higher current values during closed loop operation 0x19 hold_scale_delay (0x000000) u 23 : 0 decrement delay [# cl oc k cycles] to decrease the actual scale value by one step towards hold current. cl_downscale_delay (0x000000) decrement delay [# cl oc k cycles] to decrease the current scale value by one step towards lower current values during closed loop operation. 0x1a drv_scale_delay (0x000000) u 23 : 0 decrement delay [# cl oc k cycles] to decrease the current scale value by one step towards lower value. 0x1b boost_time (0x00000000) u 31 : 0 time [# clk cycles] after a ramp start when boost scaling is active. 0x1c cl_beta (0x0ff) 8 : 0 maximum commutation angle for closed loop regulation. set cl_beta > 255 carefully (esp. if cl_vlimit_en = 1). exactly 25 5 is recommended for best performance. cl_gamma (0xff) 23 : 16 maximum balancing angle to compensate back emf at higher velocities during closed loop regulation. 0x1d dac_addr_a (0x0000) u 15 : 0 fixed command/address which is sent via spi output before sending currenta_spi values. dac_addr_b (0x0000) 31 : 16 fixed command/address which is sent via spi output before sending current currentb_spi values. spi_switch_vel (0x0000) 23:0 velocity at which automatic cover datagrams could be sent or at which pwm - spi mode switchi ng (for tmc23x/24x) will be done automatically. 0x1e home_safety_margin (0x0000) u 15 : 0 home_ref polarity could be invalid within x_home home_safety_margin.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 96 www.trinamic.com v arious c onfiguration registe rs : closed loop , switches r/w addr reg name (default) s/u bit description 0x1f pwm_freq (0x0280) u 15 : 0 number of clock cycles for one pwm period. chopsync_div (0x0 280) 11 : 0 chopper clock divider the chopper frequency f osc : f osc = f clk /chopsync_div with 96chopsync_div818 19.16 ramp generator register s r amp generator r/w addr reg name (default) s/u bit description rw 0x20 rampmode (0x 0 ) 2 ramp_mode 1 p ositionin g : xtarget is super ior objective for velocity ramp. 0 velocity mode : vmax is superior objective for velocity ramp . 1 : 0 ramp _ type 00 h old mode : always vactual = vmax (rectangle velocity shape) . 01 t rapezoidal ramp : consideration of ac - and deceleration values for generating vactual , but no adaption of these values . 10 s - shape d ramp : consideration of all ramp values (incl. bow val ue s) for generating vactual . rw 0x21 xactual (0x0000000 0 ) s 31 : 0 current i nternal motor position [pulses]: C 2 31 xactual 2 31 C 1 r 0x22 vactual (0x0000000 0 ) s 31 : 0 current ramp generator velocity [p ulses per second] : 1 pps | vactual | clk_freq ? ? pulses (f clk = 16 mhz ? 8 mpps) r 0x23 aactual (0x0000000 0 ) s 31 : 0 current acceleration/deceleration value [p ulse s per sec 2 ] : 1 pps2 | aactual | and - 2 31 pps2 aactual 2 31 - 1 rw 0x24 vmax (0x0000000 0 ) s 31 : 0 maximum ramp generator velocity in positioning mode . target ramp generator velocity in velocity mode and hold mode. value representation: 23 digits and 8 decimal places. 4 mpps | vmax [pps] | clk_freq ? ? pulses rw 0x25 vstart (0x0000000 0 ) u 30 : 0 absolute s tart velocity in positioning mode and velocity mode value representation: 23 digits and 8 decimal places. positioning mode : if vactual = 0 and xtarget xactual : no acceleration phase for vactual = 0 ? vstart . velocity mode : if vactual = 0 and vactual vmax : no acceleration phase for vactual = 0 ? vstart . after switching off direct_sdin_mode: | vactual | = vstart if direct sdin mode is switched off & automatic_direct_sdin_switch_off = 1 . the direction is dependent on the last stpin/dirin configuration and the defined sd input parameter settings. rw 0x26 vstop (0x0000000 0 ) u 30 : 0 absolute stop velocity in positioning mode and in velocity mode . valu e representation: 23 digits and 8 decimal places. positioning mode : if vactual vstop and xtarget = xactual : vactual will be set to 0 immediately. velocity mode : if vactual vstop and vmax = 0 : vactual will be set to 0 immediately. i f vstop 0 ? no last bow phase b 4 for s - s haped ramps i f vstop is very small and positioning mode is used ? eventually long period at ramp end with vactual = vstop to reach xtarget . rw 0x2 7 vbreak (0x0000000 0 ) u 30 : 0 absolute break velocity in positioning mode and in velocity mode , bu t only for trapezoidal ramp types . value representation: 23 digits an d 8 decimal places. if | vactual | < vbreak ? | aactual | = astart / dfinal if | vactual | vbreak ? | aactual | = amax / d max if vbreak = 0 ? pure linear ramps ( amax / dmax only) . set always vbreak > vstop!
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 97 www.trinamic.com r amp generator r/w addr reg name (default) s/u bit description rw 0x2 8 amax (0x00000 0 ) u 23 : 0 s - shaped ramp type s: m aximum acceleration value. trapezoidal ramps types : a cceleration value if | vactual | vbreak or if vbreak = 0 . frequency mode : [p ulses per sec 2 ] value representation: 22 digits and 2 decimal places 250 mpps 2 amax 4 mpps 2 direct mode: ?v per cl oc k cycle: a[?v per cl oc k cycle]= amax / 2 37 amax [pps 2 ] = amax / 2 37 ? f clk 2 ( 31.25 gpps 2 at f clk = 16 mhz) rw 0x2 9 dmax (0x00000 0 ) u 23 : 0 s - shaped ramp type s: m aximum deceleration value. trapezoidal ramps types : d eceleration value if | vactual | vbreak or if vbreak = 0 . frequency mode : [p ulses per sec 2 ] value representat ion: 22 digits and 2 decimal places 250 mpps 2 dmax 4 mpps 2 direct mode: ?v per clk cycle: a[?v per clk_cycle]= dmax / 2 37 dmax [pps 2 ] = dmax / 2 37 ? f clk 2 ( 31.25 gpps 2 at f clk = 16 mhz) rw 0x2 a astart (0x00000 0 ) u 23 : 0 s - shaped ramp type s: start acceleration value. trapezoidal ramps types : acceleration value if | vactual | < vbreak frequency mode : [p ulses per sec 2 ] value representation: 22 digits and 2 decimal places 250 mpps 2 astart 4 mpps 2 direct mode: ?v per clk cycle: a[?v per clk_cycle]= astart / 2 37 astart [pps 2 ] = astart / 2 37 ? f clk 2 ( 31.25 gpps 2 at f clk = 16 mhz) after switching off direct_sdin_mode: | a actual | = a start if direct sdin mode is switched off & automatic_direct_sdin_switch_off = 1 . the direction is dependent on the astar t_sign_bit. a_sign_bit (0) 31 sign of aactual after switching off direct sdinput mode. rw 0x2 b dfinal (0x00000 0 ) u 23 : 0 s - shaped ramp type s: stop deceleration value. (only velocity mode) trapezoidal ramps types : d eceleration value if | vactual | < vbrea k frequency mode : [p ulses per sec 2 ] value representation: 22 digits and 2 decimal places 250 mpps 2 dfinal 4 mpps 2 direct mode: ?v per clk cycle: a[?v per clk_cycle]= dfinal / 2 37 dfinal [pps 2 ] = dfinal / 2 37 ? f clk 2 ( 31.25 gpps 2 at f clk = 16 mhz) rw 0x2 c dstop (0x00000 0 ) u 23 : 0 deceleration value for an automa tic linear stop ramp to vactual = 0 . dstop will be used with activated e xternal stop switches ( stopl or stopr ) if soft_stop_enable is set to 1 or with activated v irtual stop switches and virt_stop_mode is set to b10. rw 0x2 d bow1 (0x00000 0 ) u 23 : 0 bow value 1 (first bow b 1 of the acceler ation ramp) frequency mode : [p ulses per sec 3 ] value representation: 2 4 digits and 0 decimal places 1 mpps 3 bow1 16 mpps 3 direct mode: ?a per clk cycle: bow [? a per clk_cycle] = bow1 / 2 53 bow1 [pps 3 ] = bow1 / 2 53 ? f clk 3 ( 7.63 tpps 3 at f clk = 16 mhz) rw 0x2 e bow2 (0x00000 0 ) u 23 : 0 bow value 2 (second bow b 2 of the acceleration ramp) vide bow1 for value representation and conversion calculations. rw 0x2 f bow3 (0x00000 0 ) u 23 : 0 bow value 3 (first bow b 3 of the deceleration ramp) vide bow1 for value representation and conversion calculations. rw 0x 30 bow4 (0x00000 0 ) u 23 : 0 bow value 4 (second bow b 4 of t he deceleration ramp) vide bow1 for value representation and conversion calculations.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 98 www.trinamic.com r amp generator r/w addr reg name (default) s/u bit description rw 0x31 clk_freq (0x0f 42400 ) u 24 : 0 external clock f requency value f clk [hz] with 4.2 mhz f clk 30 mhz 19.17 target and compare register s t arget and compare re gisters r/w addr reg name (default) s/u bit description rw 0x32 pos_comp (0x0000000 0 ) s 31 : 0 compare position . rw 0x33 virt_stop_left (0x0000000 0 ) s 31 : 0 virtual left s top . rw 0 x34 virt_stop_right (0x00000000) s 31 : 0 virtual right stop. r w 0x35 x_home (0x00000000) s 31 : 0 current home position. r 0x36 x_latch (0x00000000) s 31 : 0 storage position for certain triggers ( circular_cnt_as_xlatch = 0) rev_cnt (0x00000000) number o f revolution during circular mode ( circular_cnt_as_xlatch = 1) w x_range (0x00000000) u 30:0 circular movement: limitation for x_actual - x_range xactual x_range - 1 rw 0x37 x_target (0x0000000 0 ) s 31 : 0 target motor position in positioning mode. set all other motion profile parameters before! 19.18 pipeline register s p ipeline registers r/w addr reg name (default) s/u bit description rw 0x38 x_pip e0 (0x00000000) s 31:0 1 st pipeline register rw 0x3 9 x_ pipe1 (0x00000000) s 31:0 2 nd pipeline register rw 0x3 a x_ pipe2 (0x00000000) s 31:0 3 rd pipeline register rw 0x3 b x_ pipe3 (0x00000000) s 31:0 4 t h pipeline register rw 0x3 c x_ pipe4 (0x00000000) s 31 :0 5 t h pipeline register rw 0x3 d x_ pipe5 (0x00000000) s 31:0 6 t h pipeline register rw 0x3 e x_ pipe6 (0x00000000) s 31:0 7 t h pipeline register rw 0x3 f x_ pipe7 (0x00000000) s 31:0 8 t h pipeline register 19.18.1 possible pipeline partitioning coming soon.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 99 www.trinamic.com 19.19 shad ow registers t arget and compare re gisters r/w addr reg name (default) s/u bit description rw 0x40 sh_reg0 (0x00000000) s 31:0 1 st shadow register rw 0x41 sh_reg1 (0x00000000) u 31:0 2 nd shadow register rw 0x42 sh_reg2 (0x00000000) u 31:0 3 rd shadow re gister rw 0x43 sh_reg3 (0x00000000) u 31:0 4 th shadow register rw 0x44 sh_reg4 (0x00000000) u 31:0 5 th shadow register rw 0x45 sh_reg5 (0x00000000) u 31:0 6 th shadow register rw 0x46 sh_reg6 (0x00000000) u 31:0 7 th shadow register rw 0x47 sh_reg7 (0x0 0000000) s/u 31:0 8 th shadow register rw 0x48 sh_reg8 (0x00000000) u 31:0 9 th shadow register rw 0x49 sh_reg9 (0x00000000) u 31:0 10 th shadow register rw 0x4a sh_reg10 (0x00000000) u 31:0 11 th shadow register rw 0x4b sh_reg11 (0x00000000) u 31:0 12 th s hadow register rw 0x4c sh_reg12 (0x00000000) u 31:0 13 th shadow register rw 0x4d sh_reg13 (0x00000000) u 31:0 14 th shadow register 19.19.1 possible shadow register partitioning coming soon.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 100 www.trinamic.com 19.20 freeze register the whole freeze register can only be written once after an active reset and before motion starts. it is always readable. f reeze r/w addr reg name (default) s/u bit description rw 0x4e dfreeze (0x00000 0 ) u 23 : 0 d eceleration value. if nfreeze switches to low the parameter is used for an automatic linear ramp stop. setting dfreeze to 0 leads to a n hard stop. value representation: [?v per clk_cycle] a[?v per clk_cycle]= dfreeze / 2 37 dfreeze [pps 2 ] = dfreeze / 2 37 ? f clk 2 ( 31.25 gpps 2 at f clk = 16 mhz) ifreeze (0x00) u 31 : 24 scaling value if nfreeze is tied low. if ifreeze=0, current active scaling value will be valid at frozen event. 19.21 clock gating enable register c lock gating r/w addr reg name (default) bit description rw 0x4f clk_gating_reg (0x0) 2 : 0 setting all bits to 1 and vactual = 0 initializes the clock gating countdown. if sleep state is active, this register is set to 0 and also the internal clock remains at low level (sleep state) . enable clock gating by setting clk_gating_en = 1
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 101 www.trinamic.com 19.22 encoder register s e ncoder registers r/w addr reg name (default) s/u bit description rw 0x50 enc_pos (0x00000000) s 31 : 0 current e ncoder position [steps]. r 0x51 enc_latch (0x00000000) s 31 : 0 latched encoder position . w enc_reset_val (0x00000000) defined reset value for enc_pos if the encoder position should be cleared to another value than 0 and an n event is recognized. r 0 x52 enc_pos_dev (0x00000000) s 31 : 0 current d eviation between xactual and enc_pos . w cl_tr_tolerance (0x00000000) u tolerated absolute tolerance between xactual and enc_pos to trigger target_reached_f and event. w 0x53 enc_pos_dev_tol (0xffffffff) u 3 1 : 0 tolerated value of |( x_actual C enc_pos )|. w 0x54 enc_in_res (0x00000000) u 30 : 0 resolution [encoder steps per revolution] of the encoder connected to the encoder inputs. r enc_const (0x00000000) encoder constant. value representation: 15 digits a nd 16 decimal places w manual_enc_const (0) 31 0 enc_const will be calculated automatically. 1 manual definition of enc_const = enc_in_res w 0x55 enc_out_res (0x00000000) u 31 : 0 resolution [encoder steps per revolution] of the serial encoder output int erface . w 0x56 ser_clk_in_high (0x00a0) u 15 : 0 high voltage level time of serial clock output [# cl oc k cycles] ser_clk_in_low (0x00a0) 31 : 16 high voltage level time of serial clock output [# cl oc k cycles] w 0x57 ssi_in_clk_delay (0x0000) u 15 : 0 ssi encoder: d elay time [# cl oc k cycles] between next data transfer after a rising edge of serial clock output (if set to 0 ? ssi_in_clk_delay = ser_clk_in_high ) sp i encoder: d elay [# cl oc k cycles] at start and end of data transfer between serial clock outpu t & negated chip select . (if set to 0 ? ssi_in_clk_delay = ser_clk_in_high ) biss_timeout (0x0000) biss encoder: biss timeout parameter at the end of a biss data transfer . ssi_in_wtime (0x0 f 0) 25 : 16 delay parameter tw [# cl oc k cycles] between two clock sequences for a multiple data transfer (of the same data). ssi recommendation: t w < 19 s. biss_in_busys (0x0 f 0) maximum evaluation time [# cl oc k cycles] of slave device during sensor modus . w 0x58 ser _ptime (0x00 19 0) u 19 : 0 ssi and spi encod er: delay time period tp [# cl oc k cycles] between two consecutive cl oc k sequences for new data request. ssi recommendation: tp > 21 s. biss_in_busyr (0x00 19 0) maximum evaluation time [# cl oc k cycles] of the slave device during register modus. crc _gen_polynom (0x 0 0) 31 : 24 crc generator polynomial.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 102 www.trinamic.com 19.24 pid and closed loop registers pid / closed loop r/w addr reg name (default) s/u bit description rw 0x59 cl_offset (0x00000000) s 31 : 0 offset between enc_pos and xactual during closed loop calibrati on. w 0x5a pid_p (0x000 0 00) u 23 : 0 proportional term of pid regulator = pid_p / 256 ? pid_e pid mode: parameter p of pi d regulator for direct velocity control (enable pid regulation; regulation_modus (1) = 1) c losed l oop mode: parameter p of pi regulator which controls maximum velocity during closed loop regulation. (set cl_vlimit_en = 1 if velocity limit during closed loop mode - regulation_modus = 01 - should be used) cl_vmax_calc_p (0x000 0 00) r pid_vel (0x00000000) s 31 : 0 current pid outpu t velocity. w 0x5b pid_i (0x000 0 00) u 23 : 0 integral term = pid_i / 256 ? pid_isum = pid_i / 256 ? pid_ e ? f clk /128 pid mode: parameter i of pi d regulator for direct velocity control (enable pid regulation; regulation_modus (1) = 1) c losed l oop mode: pa rameter i of pi regulator which controls maximum velocity during closed loop regulation . (set cl_vlimit_en = 1 if velocity limit during closed loop mode - regulation_modus = 01 - should be used) cl_vmax_calc_i (0x000 0 00) r pid_isum_rd (0x000 000 00) s 31 : 0 current pid integrator sum. pid_isum = pid_e ? f clk /128 update frequency = f clk /128 w 0x5c pid_d (0x000 0 00) u 23 : 0 pid mode: p arameter d of pid regulator. pid_e is sampled with f clk / 128 / pid_d_clkdiv . derivative term = (pid_e last C pid_e actu al ) ? pid_d (enable pid regulation; regulation_modus (1) = 1) cl_delta_p (0x000 0 00) c losed l oop mode: gain parameter which is multiplied with the current position difference to calculate the current commutation angle for higher stiffness for position maintenance. clipped at cl_beta. value representation: 8 digits and 16 decimal places real value = cl_delta_p / 2 16 example: 65536 = factor of 1 (no gain) w 0x5d pid_i_clip (0x0 0 00) u 14 : 0 pid and pi velocity regulator for closedloop mode: clipping parame ter for pid_isum . real value = pid_isum ? 2 16 ? pid_iclip (enable pid regulation; regulation_modus (1) = 1) pid_d_clkdiv (0x00) 23 : 16 pid and pi velocity regulator for closedloop mode: clock divider for d part calculation. (enable pid regulation; reg ulation_modus (1) = 1) r pid_e (0x000 000 00) s 31 : 0 current p osition deviation. w 0x5e pid_dv_clip (0x000 000 00) u 30 : 0 pid and pi velocity regulator for closedloop mode: clipping parameter for pid_vel . (set cl_vlimit_en = 1 if velocity limit during cl osed loop mode - regulation_modus = 01 - should be used or enable pid regulation; regulation_modus (1) = 1) w 0x5f pid_tolerance (0x000 0 0) u 19 : 0 pid mode: tolerated position deviation: pid_e = 0 if | pid_e | < pid_tolerance cl_toleranc e (0x00) 7 : 0 c losed l oop mode: tolerated position deviation : cl_delta_p = 65536 ( gain =1) if | enc_pos_dev | < cl_tolerance
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 103 www.trinamic.com 19.25 misc registers closed loop operation is internally processed using a 256 microstep resolution. it is possible to use any encoder resolution since it is scaled to 256 microsteps. closed loop i t is not possible with a s tep /d ir input resoluti on of less than 256 microsteps! m isc r/w addr reg name (default) s/u bit description w 0x60 fs_vel (0x000000) u 23 : 0 minimum fullstep velocity [pps]. if | va ctual | > fs_vel fullstep operation is possible. dc_vel (0x000000) minimum dcstep velocity [pps]. if | vactual | > fs_vel dcstep will be enabled cl_vmin_emf (0x000000) encoder velocity at which back emf consideration starts during closed loop opera tion. w 0x61 dc_time (0x00) u 7:0 upper pwm on - time limit for commutation (only tmc26x) set slightly above effective blank time tbl of the driver. dc_sg (0x0000) 15:8 maximum pwm on - time [# clock cycles ? dc_blktime (0x0000) 31:16 blank time [# clock cycles] after fullstep release when no signal comparison should happen (only valid for dcstep with tmc26x) cl_vadd_emf (0x000000) u 23 : 0 additional velocity value to calculate v_max_cl_emf which is the enco der velocity where back emf consideration reaches the maximum angle cl_gamma during closed loop operation. w 0x62 dc_lsptm (0x00ffffff) u 31:0 dcstep low speed timer [# clock cycles] enc_vel_zero (0x ffffff ) 23 : 0 delay time [# cl oc k cycles] after the l ast incremental encoder change to set v_enc_mean = 0. w 0x63 enc_vmean_wait (0x00) u 7 : 0 delay period [# cl oc k cycles] before the next current encoder velocity value becomes considered for mean encoder velocity calculation. set enc_vmean_ wait > 32 ( increm ental encoder only) will be set automatically to s er _ptime for ssi/spi encoder or to biss_in_busys for biss encoder ser_enc_variation (0x00) 7 : 0 multiplier for maximum permitted serial encoder variation between consecutive absolute encoder requests . (a bsolute encoder only) : maximum permitted value = enc_variation / 256 ? 1/8 ? enc_in_res (if enc_variation = 0 ? maximum permitted value = 1/8 ? enc_in_res ) enc_vmean_filter (0x0) 11 : 8 filter exponent to calculate mean encoder velocity. enc_vmean_int (0x0000) 31 : 16 encoder velocity update time [# cl oc k cycles] (incremental encoder only). minimum value is set automatically to 256 . cl_cycle (0x0000) 31 : 16 cl control cycle [# cl oc k cycles] (absolute encoder only). will be set automatically to faste st possible cycle for abn encoders w 0x6 4 synchro_set (0x00) - 6:0 set of switches for synchronization purposes (see next page for further information) r 0x65 v_enc (0x000 000 00) s 31 : 0 current encoder velocity [pps]. r 0x66 v_enc_mean (0x000 000 00) s 31 : 0 current filtered encoder velocity [pps].
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 104 www.trinamic.com m isc r/w addr reg name (default) s/u bit description w 0x67 vstall_limit (0x000 000 00) u 23 : 0 stop on stall velocity limit [pps] : only above this limit an active stall leads to a stop on stall if enabled. w 0x7c circular_dec (0x000) u 31:0 decimal places (bit31=1di git) for circular movement if one revolution is not exactly mapped to an even number of steps per revolution w 0x7d enc_comp_xoffset (0x0 00 0) u 15 : 0 start offset for triangular compensation in horizontal direction (as number b etween 0 and 1). enc_comp _yoffse t (0x00) s 23 : 16 start offset for triangular compensation in v ertical direction. |enc_comp_yoffset| 127 enc_comp_ampl (0x00) u 31 : 24 maximum amplitude for encoder compensation 19.25.1 synchronization configuration r eference switch conf iguration (0 x 64 ) r/w addr reg name bit description w 0x64 synchro_set default: 0x00 0 consider_mp1 0 mp1 input pin will be not considered for synchronization purposes. 1 mp1 input pin will be considered for synchronization purposes. 1 consider_mp2 0 mp2 inout pin will be not considered for synchronization purposes. 1 mp2 inout pin will be considere d for synchronization purposes. 2 cl_fit_for_mp2 0 cl_fit_flag will not be forwarded via mp2 inout pin 1 cl_fit_flag will be forwarded via mp2 inout pin. 3 mp2_as_wired_and 0 mp2 output function could not be used as wired - and. 1 mp2 output functio n could be used as wired - and. 4 mp2_as_wired_or 0 mp2 output function could not be used as wired - or. 1 mp2 output function could be used as wired - or. 5 rampgen_block_en 0 internal ramp generator will not be blocked if incoming synchronization signa l is interpreted as blocked. 1 internal ramp generator will be blocked if incoming synchronization signal is interpreted as blocked. 6 rampgen_block_en 0 external step control will not be blocked if incoming synchronization signal is interpreted as blo cked. 1 external step control will be blocked if incoming synchronization signal is interpreted as blocked.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 105 www.trinamic.com 19.26 transfer registers t ransfer r/w addr reg name (default) s/u bit description w 0x68 addr_to_enc (0x000 00 0 00) - 31 : 0 spi encoder only : address d ata permanently sent to get encoder angle data from the spi encoder slave device. biss and spi encoder: address data sent fr om TMC4361 to the encoder for one - time data transfer. w 0x69 data_to_enc (0x00 00 0 0 00) - 31 : 0 spi / biss config uration data sent fro m TMC4361 to the serial encoder for one - time data transfer. r 0x6a addr_from_enc (0x00 00 0 0 00) - 31 : 0 spi encoder only : r epeated request data is stored here. biss and spi encoder: spi / biss address data received from the serial encoder as response of the one - time data transfer. r 0x6b data_from_enc (0x000 0 00 00) - 31 : 0 spi / biss data r eceived from the serial encoder as response of the one - time data transfer. w 0x6c cover_low (0x000 00 0 00) - 31 : 0 lower configuration bits of spi orders which should be sent from TMC4361 t o the motor drivers via spi output. if automatic cover transfer is enabled (automatic_cover = 1 and resulting cover_data_length 32), cover_low will be sent if | vactual | crosses spi_switch_vel downwards . w 0x6d cover_high (0x000 00 0 00) - 31 : 0 upper configuration bits of spi orders which should be sent from TMC4361 t o the motor drivers via spi output. if automatic cover transfer is enabled (automatic_cover = 1 and resulting cover_data_length 32), cover_ high will be sent if | vactual | crosses spi_switch_vel upwards . r 0x6e cover_drv_low (0x000 0 00 00) - 31 : 0 lower configuration bits of spi response received from the motor driver connected to the spi output. r 0x6f cover _ drv_high (0x000 0 00 00) - 31 : 0 upper configuration bits of spi response rece ived from the motor driver connected to the spi output.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 106 www.trinamic.com 19.27 sinlut registers s in lut r/w addr reg name (default) s/u bit description w 0x7 0 mslut[0] (0x aaaab554 ) - 31 : 0 each bit defines the difference between consecutive values in the microstep look - up ta ble mslut (in combination with mslutsel). 0x7 1 mslut[ 1 ] (0x 4a9554aa ) 0x7 2 mslut[ 2 ] (0x 24492929 ) 0x7 3 mslut[3 ] (0x 10104222 ) 0x7 4 mslut[4 ] (0x fbffffff ) 0x7 5 mslut[5 ] (0x b5bb777d ) 0x7 6 mslut[6 ] (0x 49295556 ) 0x7 7 mslut[7 ] (0x0 0 4 04222 ) w 0x78 mslutsel (0x ffff8056 ) - 31 : 0 definition of the four segments within each quarter mslut wave. r 0x79 mscnt (0x 0 00) u 9 : 0 current step position of the sine value. w msoffset (0x000) 9:0 microstep offset for pwm mode (tmc23x/24x only) r 0x7a currenta (0x000) s 8 : 0 actual current value of coila (sine values). currentb (0x000) s 24 : 16 actual current value of coilb (sine90_120 values). r 0x7b currenta_spi (0x000) s 8 : 0 actual current value of coila (sine values). currentb_spi (0x00 0) s 24 : 16 actual current value of coilb (sine90_120 values). r 0x7c scale_param (0x000) u 8 : 0 actual used scale parameter. w 0x7e start_sin (0x00) u 7 : 0 start value for sine waveform start_sin90_120 (0x f7 ) u 23 : 16 start value for cosine waveform d ac_offset (0x00) u 31 : 24 offset for absolute sine and cosine values which will be forwarded via spi output as dac output values .
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 107 www.trinamic.com 19.28 version registers v ersion r/w addr reg name (default) s/u bit description r 0x7f version no (0x0001) u 15 : 0 current tmc43 61 version number
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 108 www.trinamic.com 20 absolute maximum ratings the maximum ratings may not be exceeded under any circumstances. operating the circuit at or near more than one maximum rating at a time for extended periods shall be avoided by application design. parameter (v cc = 3.3v nominal ? test_mode = 0v) symbol min max unit supply voltage v cc 3.0 3.6 v input voltage io v in - 0.3 3 .6 v parameter (vcc = 5v nominal ? test_mode = 1.8v) symbol min max unit supply voltage v cc 4.8 5.2 v input voltage io v in - 0.3 5.2 v 21 el ectrical characteristics 21.1 dc characteristics operating conditions dc characteristics contain the spread of values guaranteed within the specified supply voltage range unless otherwise specified. typical values represent the average value of all parts measur ed at +25c. temperature variation also causes stray to some values. a device with typical values will not leave min/max range within the full temperature range. parameter symbol conditions min typ max unit extended temperature range t com - 4 0 c 125 c nominal core voltage v dd 1.8 v nominal io voltage v dd 3.3 / 5 .0 v nominal input voltage v in 0.0 3.3 / 5 .0 v input voltage low level v inl v dd = 3.3v / 5v - 0.3 0.8 / 1. 2 v input voltage high level v inh v dd = 3.3v / 5v 2. 3 / 3.5 3.6 / 5. 2 v input with pull - down v in = v dd 5 30 110 a input with pull - up v in = 0v - 110 - 30 - 5 a input low current v in = 0v - 10 10 a input high current v in = v dd - 10 10 a output voltage low level v outl v dd = 3.3v / 5v 0.4 v output voltage high level v o uth v dd = 3.3v / 5v 2.64 / 4.0 v output driver strength i out_drv v dd = 3.3v / 5v 4.0 ma
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 109 www.trinamic.com 21.2 power dissipation parameter symbol conditions min typ max unit static power dissipation pd stat all inputs at vdd or gnd v dd = 3.3v / 5v 1. 1 / 1. 7 mw dynamic power dissipation pd dyn all inputs at vdd or gnd f clk variable v dd = 3.3v / 5v 2. 3 / 3. 7 mw / mhz total power dissipation pd f clk = 16 mhz v dd = 3.3v / 5v 37.9 / 60.3 mw
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 110 www.trinamic.com 21.3 general io timing parameters parameter symbol conditions min typ max unit o peration frequency f clk f clk = 1 / t clk 4.2 *) 16 30 mhz clock period t clk rising edge to rising edge 33.5 62.5 ns clock time low 16 .5 ns clock time high 16 .5 ns clk i nput signal rise time t rise_in 2 0 % to 8 0 % 20 ns clk i nput signal fall t ime t fall_in 8 0 % to 2 0 % 20 ns output signal rise time t rise_out 2 0 % to 8 0 % load 32 pf 3.5 ns output signal fall time t fall_out 80 % to 2 0 % l oad 32 pf 3.5 ns setup time for spi input signals in synchronous design t su relative to ris ing clk edg e 5 ns hold time t hd relative to ris ing clk edge 5 ns *) the lower limit for f clk refers to the limits of the internal unit conversion to physical units. the chip will also operate at lower frequencies.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 111 www.trinamic.com 22 modifi cations as regards TMC4361 (old vers ion) 1. limitations as regards the usage of trapezoidal ramps are obsolete 2. s - ramps: erroneous behavior by setting vmax=0 during positioning ramp is fixed ? for security reasons, keep old handling (switch to velocity mode, then set vmax = 0, then wait for vatu al=0, then switch to positioning mode again 3. stpin/dirin support with adjustable direct and indirect external control including free adjustable gearing factor (and selectable input filter settings) 4. dcstep support for tmc26x and tmc21xx /51xx 5. extensive synchr onization support: a. automatic switch between slave mode (external control) and internal ramp mode to ease slave/master switches during an active ramp b. intr and target_reached pins with selectable pu/pd output functionality for connecting several motion contr ollers c. masterless start signal synchronization mode selectable 6. substantial expansion of pipeline possibilities: a. besides xtarget, pos_comp, gear_ratio and general_conf selectable for pipeline usage (ease also synchronization) 7. shadow registers available for pipelining and synchronizing ramp parameters. 8. circular movement (limited range for xactual: - x_range <= xactual < x_range) with automatic overflow calculation. extra settings are provided to support also number of steps per revolutions which are not even integers (uneven numbers and decimal places possible) a. virtual stop position could be used to define a blocking area in the circle. the path from xactual to xtarget will not cross this area. b. automatic count of executed revolutions (=rev_cnt) c. abn support of circular movements 9. velocity mode for closed loop operation mode 10. automatic fullstep switching for tmc21xx /51xx in s/d mode 11. automatic pwm switching for tmc24x (low velocity: pwm mode, higher: spi mode) 12. target_reached generation is now also dependent on posit ion deviation during closed loop operation 13. after starting with vstart, astart is also available for another starting acceleration value than amax 14. motor direction reversible by setting a switch 15. compare possibilities expanded a. xactual/enc_pos vs pos_comp/x_l atch/x_home or pos_comp vs rev_cnt 16. x_home now read/write, not only readable 17. enc_const now read/write, not only readable (if automatic enc_const calculation is not feasible) 18. enc_pos could now set to any defined value if enc_pos should be cleared at n - event 19. encoder velocity calculation is now also available for serial encoders 20. sleep timer event exchanged with rst event 21. version register available 22. spi mode available where only cover datagrams will be sent, even during motion 23. velocity dependent spi cover datagra m transfer
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 112 www.trinamic.com 23 layout e xample figure 23 . 1 internal circuit diagram for layout example figure 23 . 2 components (assembly for application with encoder)
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 113 www.trinamic.com 1 - top l a yer (assembly side) 2 - inner l ayer (gnd) 3 - inner l ayer (supply vs) 4 - bottom l ayer f igure 23 . 3 layout example
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 114 www.trinamic.com 24 package mechanical data 24.1 dimensional drawing s attention: drawings not to scale. all va lues in millimeters. 24.2 package codes type package temperature range code & marking tmc 4361 qfn 40 (rohs) - 40c ... +125c tmc 4361 - l a parameter ref min nom max total thickness a 0.8 0.85 0.9 stand off a1 0 0.035 0.05 mold thickness a2 - 0.65 0.67 lead frame thickness a3 0.203 ref lead width b 0.2 0.25 0.3 body size x d 6 bsc body size y e 6 bsc lead pitch e 0.5 bsc exposed die pad size x j 4.52 4.62 4.72 exposed die pad size y k 4.52 4.62 4.72 lead length l 0.35 0.4 0.45 package edge tolerance aaa 0.1 mold flatness bbb 0.1 coplanarity ccc 0.08 lead offset ddd 0.1 exposed pad offset eee 0.1 figure 24 . 1 dimensional drawings
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 115 www.trinamic.com 25 disclaimer trinamic motion control gmbh & co. kg does not authorize or warrant any of its products for use in life support systems, withou t the specific written consent of trinamic motion control gmbh & co. kg. life support systems are equipment intended to support or sustain life, and whose failure to perform, when properly used in accordance with instructions provided, can be reasonably ex pected to result in personal injury or death. information given in this data sheet is believed to be accurate and reliable. however no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third p arties which may result from its use. specifications are subject to change without notice. all trademarks used are property of their respective owners. 26 esd sensitive device the TMC4361 is an esd sensitive cmos device sensitive to electrostatic discharg e. take special care to use adequate grounding of personnel and machines in manual handling. after soldering the devices to the board, esd requirements are more relaxed. failure to do so can result in defect or decreased reliability.
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 116 www.trinamic.com 27 table of f igures figure 1.1 basic application block diagram ................................ ................................ ................................ ..................... 5 figure 2.1 pinning (top view) ................................ ................................ ................................ ................................ ............... 6 figure 3.1 how to connect the TMC4361 (vcc = 3.3v) ................................ ................................ ................................ .. 8 figure 3.2 how to connect the TMC4361 (vcc = 5v) ................................ ................................ ................................ ..... 8 figure 3.3 TMC4361 wi th tmc26x stepper driver in spi mode or s/d mode ................................ ......................... 9 figure 3.4 TMC4361 with tmc248 stepper driver in spi mode ................................ ................................ .................. 9 figure 3.5 TMC4361 with tmc21xx stepper driver in spi mode or s/d mode ................................ ....................... 9 figure 5.1 spi timing ................................ ................................ ................................ ................................ ............................ 12 figure 6.1 step/dir input pin filter settings will be derived from the reference input filter group: sr_sdin = 6, filt_l_sdin = 3 (other input filter groups: sr_enc_in = 5, filt_l_enc_in = 6, sr_ref = 6, filt_l_ref = 3, sr_s = 2, filt_l_s = 4, sr_enc_out = 0, filt_l_enc_out = 0) ................................ .................. 14 figure 6.2 reference input pins: sr_ref = 1, filt_l_ref = 1 ................................ ................................ .................... 14 figure 6.3 start input pin: sr_s = 2, filt_l_s = 0 ................................ ................................ ................................ ..... 15 figure 6.4 encoder interface input pins: sr_enc_in = 0, filt_l_enc_in = 7 ................................ ....................... 15 figure 8.1 rectangle shaped ramp type ................................ ................................ ................................ .......................... 20 figure 8.2 trapezoidal shaped ramp type ................................ ................................ ................................ ...................... 20 figure 8.3 s - shaped ramp without initial and final acceleration/deceleration values ................................ ...... 21 figure 8.4 s - shaped ramp type with initial acceleration and final deceleration value for b1 and b4 ........ 21 figure 8.5 trapezoidal and s - shaped ramps using vstart ................................ ................................ ...................... 22 figure 8.6 trapezoidal and s - shaped ramps using vstop ................................ ................................ ........................ 22 figure 8.7 trapezoidal and s - shaped ramps using vstart and vstop ................................ ................................ 22 figure 8.8 s - shaped ramps using vstart > 0 and use_astart_and_vstart = 1 . as a result, section b 1 will be passed through, although vstart is used. ................................ ................................ ................................ ............. 23 figu re 10.1 home_ref monitoring and home_error_flag ................................ ................................ ..................... 29 figure 10.2 circular movement ( x_range = 300), the green arrow depicts the path which is chosen for positioning: ................................ ................ a) shortest path selection b) consideration of blocking zones 32 figure 11.1 start example 1 ................................ ................................ ................................ ................................ ................ 36 figure 11.2 start example 2 ................................ ................................ ................................ ................................ ................ 37 figure 11.3 start example 3 ................................ ................................ ................................ ................................ ................ 37 figure 11.4 single - level shadow register option ................................ ................................ ................................ .......... 38 figure 11.5 dou ble - stage shadow register option 1 ................................ ................................ ................................ ... 38 figure 11.6 double - stage shadow register option 2 ................................ ................................ ................................ ... 39 figure 11.7 double - stage shadow registe r option 3 ................................ ................................ ................................ ... 39 figure 11.8 usage of the shadow_miss_cnt parameter to delay the shadow register transfer for several internal start signals ................................ ................................ ................................ ................................ .............. 40 figure 11.9 flexible target pipeline ................................ ................................ ................................ ................................ .. 41 figure 11.10 one pipeline with a) 8 stages and b) 6 stages behind the target register ................................ . 42 figure 11.11 two pipelines with a) each 4 stages and b) 3/2 stages behind the target registers .............. 43 figure 11.12 a) two pipelines with 3 stages and one pipeline with 2 stages b) two pip elines with 2 stages and one pipeline with 2 stages, but without writing data back ............... 43 figure 11.13 four pipelines with 2 stages with a) and without b) writing back data ................................ ..... 43 figure 12.1 lut programming example ................................ ................................ ................................ ......................... 46 figure 12.2 wave showing segments with all possible base inclinations (highest inclination first) .......... 47 figure 12.3 spi output datagram timing (cdl C cover_data_length) ................................ ................................ ..... 49 figure 12.4 cover data register composition (cdl C cover_data_length) ................................ .............................. 50 figure 12.5 scaling: example 1 ................................ ................................ ................................ ................................ .......... 57 figure 12.6 scaling: example 2 ................................ ................................ ................................ ................................ .......... 57 figure 14.1 calculation of pwm duty cycles ................................ ................................ ................................ .................. 59 figure 15.1: dcstep extended application operation area ................................ ................................ ......................... 61 figure 15.2: velocity p rofile with impact by overload situation ................................ ................................ ............. 62 figure 16.1 outline of abn signals of an incremental encoder ................................ ................................ .............. 66 figure 16.2 ssi signal s with ssi_in_clk_delay = ser_clk_in_high when ssi_in_clk_delay=0 ................... 68 figure 16.3 ssi signals with ssi_in_clk_delay for compensating processing time and long wires ......... 68 figure 16.4 supported spi encoder data transfer modes ................................ ................................ .......................... 70 figure 16.5 calculation of the output angle by setting cl_delta_p properly. ................................ ................... 73 figure 16.6 current scaling in with closed loop ................................ ................................ ................................ .......... 75 figure 16.7 current scaling timing behavior ................................ ................................ ................................ ................. 75
TMC4361 datasheet (rev. 2.68 / 201 5 - apr - 14 ) preliminary 117 www.trinamic.com figure 16.8 calculation of the current load angle cl_gamma ................................ ................................ ................. 76 figure 16.9 implemented triangular function to compensate for encoder misalignments ............................ 77 figure 17.1 example for ssi output configuration ................................ ................................ ................................ ....... 78 figure 18.1 manual clock gating and manual wake up. ................................ ................................ ............................. 79 figure 18.2 automatic clock gating ................................ ................................ ................................ ................................ .. 80 figure 23.1 internal circuit diagram for layout example ................................ ................................ ......................... 112 figure 23.2 components (asse mbly for application with encoder) ................................ ................................ ...... 112 figure 23.3 layout example ................................ ................................ ................................ ................................ .............. 113 figure 24.1 dimensional drawings ................................ ................................ ................................ ................................ . 114 28 revision history 28.1 document revision s version date author hs = hagen s?mrow sk = stephan kubisch sd = sonja dwersteg descrip tion 2 .52 2014 - apr - 09 hs transfer from TMC4361old manual (v1.04) and first adjustments and explanations of the extended feature set 2 .5 3 2014 - aug - 04 hs test of new fms: power consumption increases slightly ? power safety margins after new measurement inc reased 2 .6 0 2014 - aug - 20 hs further adaptations till chapter 12.5 2.61 2014 - aug - 25 hs register overview updated modifications (as regards TMC4361old) overview generated 2.62 2014 - aug - 27 hs problems with virt_stop_mode=00 and s - ramps occurred during bow phase b1 and b12 ? virt_stop_mode=00 prohibited for now further investigations in progress until a workaround is achieved furthermore, insert attention for not changing rampmode if v 0 (esp. changing from velocity to pos mode is crucial) 2.62 2014 - sep - 27 hs update of 0x63 register double assignments for incremental ? ? absolute encoders 2.62 2014 - sep - 30 hs product key newly assigned to TMC4361 - la (former key: TMC4361 - li) t o exhibit the extended temperature range 2.65 2014 - oct - 02 hs freezed to frozen (correct now) changed limits for on - the - fly changes expressed vmax=0 failure added 2.65 2014 - oct - 02 hs vdd5 changed to vcc - images adapted - electrical spec adapted - remarks added for vcc = 5v ? test_mode have to be connect to vdd1v8! 2.65 2014 - nov - 20 hs beautifying, some minor adaptations 2.65 2014 - dec - 01 hs hint for 220ohm resistors in series if start is connected to another TMC4361 2.6 6 2015 - jan - 2 1 hs limita tions for shadow r amp transfer during motion added 2.66 2015 - feb - 03 hs hints for enc_wait and v_enc_filter added 2.6 7 2015 - apr - 01 hs register description s corrected 2.68 2015 - apr - 14 hs changed cl_beta=255 (from 256) for best performance table 28 . 1 document revisions

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